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CXL Glossary

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DDR5 vs DDR4 DRAM – All the Advantages & Design Challenges

Last updated on: September 7, 2022 On July 14th, 2021, JEDEC announced the publication of the JESD79-5 DDR5 SDRAM standard signaling the industry transition to DDR5 server and client dual-inline memory modules (DIMMs). DDR5 memory brings a number of key performance gains to the table, as well as new design challenges. Computing system architects, designers, and […]

AI Accelerates HBM Momentum

In a recent EE Times article, Gary Hilson notes that high bandwidth memory (HBM) deployments are becoming more mainstream due to the massive growth and diversity in artificial intelligence (AI) applications. “HBM is [now] less than niche. It’s even become less expensive, but it’s still a premium memory and requires expertise to implement,” writes Hilson. […]

[DEMO] DDR5 Server DIMM buffer chipset

[Demo]: Discover why Rambus DDR5 Server DIMM buffer chipset is the industry’s first functional silicon targeted for next-generation DDR5. in this video how the Rambus DDR5 memory interface chipset helps designers harness the full advantages of DDR5 while dealing with the signal integrity challenges of higher data, CA, and clock speeds. Contact Sales

Compute Express Link (CXL): All you need to know

In this blog post, we take an in-depth look at Compute Express Link ™ (CXL) 2.0, an open standard cache-coherent interconnect between processors and accelerators, smart NICs, and memory devices. We explore how CXL is helping data centers more efficiently handle the yottabytes of data generated by artificial intelligence (AI) and machine learning (ML) applications. […]

PCIe 6.0 Controller

Interface IP PCIe 6.0 Controller The PCI Express® (PCIe®) 6.0 Controller is configurable and scalable controller IP designed for ASIC implementation. The controller supports the PCIe 6.0 specification, including 64 GT/s data rates, PAM4 signaling, FLIT mode, and L0p power state. The PCIe 6.0 architecture will be essential for SoC designers creating next-generation chips that […]

Rambus Advances New Era of Data Center Architecture with CXL™ Memory Interconnect Initiative

Launches research and development effort to drive architectural shift in data centers with solutions for memory expansion and pooling that enable disaggregated and composable server architectures Combines unique expertise in high-speed interfaces, embedded security and server memory buffers to develop breakthrough solutions for next-generation data centers Leverages critical building blocks to be provided by PLDA […]

What are the security implications of quantum computing?

Helena Handschuh, a Rambus Security Technologies fellow, recently wrote an article for Semiconductor Engineering that explores the security implications of quantum computing. As Handschuh notes, the U.S. Government has awarded $625 million in funding to create five quantum information research centers. “Industry and academic institutions will contribute $300 million toward this effort with the remainder […]

Three Top Semiconductor Tech Trends for 2021

As a momentous 2020 fades into the history books, 2021 is expected to be a year of growth and evolution for the semiconductor industry across multiple market segments. Firstly, DDR5 DRAM is slated to enter volume production by the end of 2021, with initial deployments targeting hyperscale data centers. Secondly, AI/ML neural networks – which […]

AI Requires Tailored DRAM Solutions: Part 2

Written by Rambus Press Frank Ferro, Senior Director Product Management at Rambus, and Shane Rau, Senior Research Executive at IDC, recently hosted a webinar that explores the role of tailored DRAM solutions in advancing artificial intelligence. Part one of this four-part series reviewed a range of topics including the interconnected system landscape, the impact of […]