Found 55 Results

Taking the Show on the Road

https://www.rambus.com/blogs/taking-the-show-on-the-road/

Starting later this month, Rambus will host a series of lunch & learns around the globe entitled “Securing Electronic Systems at their Foundation.”  These technical sessions are designed for engineering, product, and program management staff at both defense and commercial OEMs. Interactive in nature, they will address specific security issues facing attendees. Topics that attendees […]

Presenting Multiple Roots of Trust Across the World

https://www.rambus.com/blogs/presenting-multiple-roots-of-trust-across-the-world/

Our friends at SiFive have been hosting a worldwide series of technical seminars, and Rambus has joined them for a number of these to present our CryptoManager Root of Trust secure co-processor.  We highlight how our Root of Trust forms the anchor of hardware-based security, and specifically how we enable multiple roots of trust. A […]

Helena Handschuh’s Article: RISC-V, DARPA Advance Security

https://www.rambus.com/blogs/helena-handschuhs-article-risc-v-darpa-advance-security/

Helena Handschuh wrote a recent article in EE Times stating that “with the proliferation of intelligent devices, the industry needs new robust security approaches instead of trying to fix the cracks in existing designs.” Handschuh is chair of the RISC-V Foundation’s security standing committee and a Fellow at Rambus. Titled “RISC-V, DARPA Advance Security,” the […]

Rambus’ Ben Levine talks IoT security and cryptography with EDA Café

https://www.rambus.com/blogs/rambus-ben-levine-talks-iot-security-and-cryptography-with-eda-cafe/

Ben Levine, Senior Director of Product Marketing at Rambus, recently sat down with Sanjay Gangal of EDA Café to discuss IoT security and cryptography. According to Levine, security should be embedded in every chip. More specifically, says Levine, a separate hardware-based security core can help protect both the SoC itself and the system it powers. […]

EE Times Article Series Touts RISC-V

https://www.rambus.com/blogs/ee-times-article-series-touts-risc-v/

Rich Quinnell, veteran semiconductor industry reporter, has written an EE Times article with the headline, RISC-V on the Verge of Broad Adoption. This is one in a series of RISC-V articles EE Times has posted within the last several months.  Each piece lauds the promises RISC-V holds to become a dominant factor in the industry. […]

The Next Vulnerability: Looking Back on Meltdown and Spectre One Year Later

https://www.rambus.com/blogs/the-next-vulnerability-looking-back-on-meltdown-and-spectre-one-year-later/

Around this time last year, two vulnerabilities known as Meltdown and Spectre became public. Discovered independently by multiple research teams, each flaw exposed critical vulnerabilities across a wide range of modern processors, including ones from major chip makers Intel and AMD, as well as several designs based on the ARM architecture. Unsurprisingly, Meltdown and Spectre […]

Rambus Reports Fourth Quarter and Fiscal Year 2018 Financial Results

https://www.rambus.com/fourth-quarter-2018-fiscal-year-2018-financial-results/

Fourth quarter GAAP revenue of $68.5 million; revenue under ASC 605 would have been $102.0 million, in line with expectations; $35.1 million in cash provided by operating activities Record product revenue in 2018 for IP cores and server DIMM chips with wins at Tier 1 customers in data center and communications segments worldwide CryptoManager platform […]

India Tech Pursues RISC-V ISA

https://www.rambus.com/blogs/india-tech-pursues-risc-v-isa/

EE Times India reports that the RISC-V instruction set architecture (ISA) has made significant progress in that country. It says that researchers at Indian Institute of Technology, Madras (IIT-M) have designed and booted up India’s first microprocessor dubbed “Shakti” (meaning power), which is targeted at mobile computing and other devices. The Shakti family of processors was […]

Six Top Rambus IP Core Training Sessions Slated for DesignCon 2019

https://www.rambus.com/blogs/six-top-rambus-ip-core-training-sessions-slated-for-designcon-2019/

Some of the top Rambus technical experts will hold forth at DesignCon 2019 in a full-day sponsored training session on Wednesday, January 30. Plus, the Rambus booth #837 will demonstrate the company’s developments in GDDR6, as well as its comprehensive suite of Ethernet, PCIe, DDR, and HBM IP cores for today’s most challenging data center and […]

Rambus Highlights CryptoManager Root of Trust At RISC V Summit – 2018

https://www.rambus.com/blogs/rambus-highlights-cryptomanager-root-of-trust-at-risc-v-summit-2018/

We will be showcasing our CryptoManager Root of Trust at the RISC-V Summit on December 3-6,2018, at the Santa Clara Convention Center.. CryptoManager Root of Trust is a fully programmable root of trust core that provides secure processing based on RISC-V architecture.  The CryptoManager Root of Trust or CMRT incorporates industry-leading hardware security and anti-tamper capabilities and […]

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