Rambus Highlights CryptoManager Root of Trust At RISC V Summit -2018
This entry was posted on Friday, November 30th, 2018.
We will be showcasing our CryptoManager Root of Trust at the RISC-V Summit on December 3-6,2018, at the Santa Clara Convention Center.. CryptoManager Root of Trust is a fully programmable root of trust core that provides secure processing based on RISC-V architecture. The CryptoManager Root of Trust or CMRT incorporates industry-leading hardware security and anti-tamper capabilities and is designed for applications ranging from networking to automotive to IoT.
One demo explains to show attendees real world device examples in a connected home that executes applications securely on the same processor without having to trust other entities. Each connected home application will have access to only specified features and resources that are cryptographically isolated from other applications.
The other is a joint demonstration with Rambus and SiFive, explaining a secure boot application. Here, a SiFive RISC V processor is integrated with the Rambus CryptoManager Root of Trust (CMRT) to provide a complete solution for both general purpose and secure processing. This demo showcases how the CMRT is used to provide secure boot functionality that ensures the SiFive processor in the system only boots images from a trusted source. This provides a foundation for security of the whole system.
Dr. Martin Scott, CTO and SVP/GM of Cryptography at Rambus, will present on the panel “RISC-V Security Ecosystem: Open for Business.” on Tuesday, December 4, 2018 at the Meeting Room 209/210 from 3:40pm – 4:20pm local time. The session will discuss security issues faced by customers during implementation. Additionally they will also cover holistic test and verification best practices at the platform level.
In addition, Helena Handschuh, Rambus Fellow and Chair of the RISC-V Foundation Security Standing Committee, and other recognized security experts, will present on the panel “Opportunities and Challenges in Security for Open Source Hardware.” on Wednesday, December 5, 2018 at the Exhibit Hall A-1 from 10:40am – 11:20am local time. The focus of the panel discussion is on newly emerging threats on processors and the advantages of the RISC V approach to counter these threats.
Lastly, Elke De Mulder, Embedded Security Researcher at Rambus and Michael Hutter, Senior Principal Engineer at Rambus will discuss “How to Protect RISC-V Against Side-Channel Attacks? “ on Wednesday, December 5, 2018 at the Meeting Room 209/210 from 2:10 pm to 2:30 pm local time. The solution integrates side-channel analysis countermeasures into a RISC V implementation and protects against any first order power or electromagnetic attacks while keeping implementation costs as low as possible.
Join Rambus at booth #103 or schedule a meeting with one of our security experts to discover more about Rambus Security solutions for applications from networking to automotive to IoT. To learn more, visit https://www.rambus.com/event/risc-v-summit/. For more information on Rambus solutions, visit rambus.com/security.