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PCIe 7.0 Retimer Controller with CXL Support Contact Us PCI Express® (PCIe®) 7.0 links operating at 128 GT/s using PAM4 signaling have a reach of up to 13 inches at nominal conditions on standard PCBs. Extending trace routing beyond this distance results in higher first bit error rates (FBER) and reduced link efficiency due to […]
PCIe 7.0 Controller Contact Us The Rambus PCI Express® (PCIe®) 7.0 Controller is a configurable and scalable design for ASIC implementations. Optimized for high-bandwidth efficiency at data rates up to 128 GT/s, the controller delivers maximum performance for Data Center, Edge, AI/ML and HPC applications. It is backward compatible to the PCIe 6.0 and 5.0, […]
The relentless innovation in Artificial Intelligence (AI) and High-Performance computing (HPC) demands a cutting-edge hardware infrastructure capable of handling unprecedented data loads. To overcome these challenges and usher in a new era of performance, Rambus is proud to announce the launch of our PCI Express® (PCIe®) 7.0 IP portfolio, encompassing a comprehensive suite of IP […]
The Rambus PCIe 7.0 Retimer Controller provides a complete digital data path solution that delivers best-in-class latency, power and area, and accelerates the time-to-market for PCIe 7.0 retimer chips.
The Rambus PCI Express® (PCIe) 7.0 Switch is a customizable, multiport embedded switch for PCIe designed for ASIC and FPGA implementations. It enables the connection of one upstream port and multiple downstream ports as a fully configurable interface subsystem. It is backward compatible to PCIe 5.0.
The Rambus PCI Express® (PCIe) 7.0 Controller with AXI is a configurable and scalable design for ASIC implementations. It is backward compatible to PCIe 6.2 and 5.0, and compatible with version 6.x of PHY Interface for PCI Express (PIPE) specification and the AMBA® AXI™ Protocol Specification.
The Rambus PCIe 7.0 Controller is configurable and scalable controller IP designed for ASIC implementations. It is backward compatible to the PCIe 6.0 and 5.0, as well as version 6.2.1 PHY Interface for PCI Express (PIPE) specification.
This episode of “Ask the Experts” features a discussion on High Bandwidth Memory (HBM) with memory experts Frank Ferro and Nidish Kamath. The conversation focused on the role of HBM in today’s computing landscape, particularly for data center, AI, and High-Performance Computing (HPC) applications. The experts highlighted the advantages of HBM3E, including higher memory bandwidth, […]
https://youtu.be/cgyBdINj6sI In this episode of Ask the Experts, we discuss HBM3E memory with Nidish Kamath, director of product management for memory interface IP at Rambus, and Frank Ferro, group director of memory and storage IP at Cadence. Topics discussed include: The role HBM plays in today’s computing landscape Reasons why we’ve seen such a rapid […]
MIPI® Alliance technology has helped enable the dramatic growth of the mobile phone market. The function and capabilities of MIPI interface solutions have grown dramatically as well. MIPI DSI-2SM has become the leading display interface across a growing range of products including smartphones, AR/VR, IoT appliances and ADAS/autonomous vehicles. As the application space has expanded, […]
