At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
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HBM3 Memory: Break Through to Greater Bandwidth
https://go.rambus.com/hbm3-memory-break-through-to-greater-bandwidth#new_tabAI/ML’s demands for greater bandwidth are insatiable driving rapid improvements in every aspect of computing hardware and software. HBM memory is the ideal solution for the high bandwidth requirements of AI/ML training, but it entails additional design considerations given its 2.5D architecture. Now we’re on the verge of a new generation of HBM that will […]
PCIe 5.0 Controller IP on FPGAs: Current and Future Use Cases
https://www.rambus.com/blogs/pcie5-controller-fpgas/Rambus announced this week that it demonstrated for the first time a PCI Express 5.0 Controller IP (PCIe 5 Controller) operating at 32 GT/s on a leading FPGA platform. “We’ve achieved a new industry benchmark with the demonstration of our PCIe 5.0 Controller operating at 32 GT/s on popular FPGA platforms,” said Scott Houghton, general […]
Rambus True Random Number Generator Certified to NIST SP 800-90B Standard
https://www.rambus.com/blogs/rambus-true-random-number-generator-certified-to-nist-sp-800-90b-standard/Cryptography depends on entropy. More specifically, every cryptographic protocol requires a source of non-deterministic (random) data to seed its security algorithms. While entropy is everywhere and, per the second law of thermodynamics, always increasing, it is exceedingly hard to create an unpredictable, statistically independent, uniformly distributed and protected source of data. In other words, creating a true random number generator is quite […]
Rambus Demonstrates Industry-first PCIe® 5.0 Digital Controller IP for FPGAs
https://www.rambus.com/rambus-demonstrates-industry-first-pcie5-digital-controller-ip-for-fpgas/Highlights: Achieves industry-first demonstration of 32 GT/s PCIe 5.0 Digital Controller IP operation on leading FPGA platforms Expands use models for FPGAs by enabling multi-instance, PCIe 5.0 switching and bridging at 32 GT/s speeds Enhances performance and capabilities of FPGAs for use in emulation and prototyping, test and measurement, aerospace and defense, and storage and […]
Rambus Design Summit Featured Speaker: Steven Woo
https://www.rambus.com/blogs/rambus-design-summit-featured-speaker-steven-woo/Another week, another Rambus Design Summit wrap up! Over the coming weeks, we will be featuring sessions from RDS 2021 with key takeaways and speaker highlights. This week we are featuring… Session Topic: Emerging Compute Architectures for the Evolving Data Center Rambus fellow and distinguished inventor, Dr. Steven Woo, kicked off the Rambus Design Summit […]
CXL 2.0 Controller Product Brief
https://go.rambus.com/cxl2-controller-product-brief#new_tabThe Rambus Compute Express Link (CXL) 2.0 Controller leverages a silicon-proven PCIe 5.0 controller architecture for the CXL.io path, and adds CXL.cache and CXL.mem paths specific to the CXL standard.
CXL 2.0 Controller with AXI Product Brief
https://go.rambus.com/cxl2-controller-axi-product-brief#new_tabThe Rambus Compute Express Link (CXL) 2.0 Controller with AXI leverages a silicon-proven PCIe 5.0 controller architecture for the CXL.io path, and adds CXL.cache and CXL.mem paths specific to the CXL standard. This controller offers support of the AMBA AXI, CPI and AMBA CXS-B protocol specifications.
PCIe 5.0 Controller with AXI Product Brief
https://go.rambus.com/pcie5-controller-axi-product-brief#new_tabThe Rambus PCIe 5.0 controller with AXI is designed for maximum performance and ease of use for PCI Express (PCIe) 5.0 applications. It comprises a complete SerDes subsystem with the Rambus PCIe 5.0 PHY or can integrate with PIPE 5.x-compliant 3rd-party PHYs. The controller is backwards compatible with PCIe 4.0, and 3.1/3.0.
PCIe 5.0 Multi-port Switch Product Brief
https://go.rambus.com/pcie5-multi-port-switch-product-brief#new_tabThe Rambus PCIe 5.0 Multi-port Switch is a customizable, multiport embedded switch for PCIe designed for ASIC and FPGA implementations enabling the connection of one upstream port and up to 31 downstream ports.
PCIe 4.0 Controller with AXI Product Brief
https://go.rambus.com/pcie4-controller-axi-product-brief#new_tabThe Rambus PCIe 4.0 Controller with AXI is designed to achieve maximum PCI Express (PCIe) 4.0 performance with great design flexibility and ease of integration. It comprises a complete SerDes subsystem with the Rambus PCIe 4.0 PHY or can integrate with PIPE 4.2-compliant 3rd-party PHYs. The controller is backwards compatible with PCIe 3.1/3.0.
