The proliferation of connected devices has significantly increased the amount of data being captured, moved and analyzed. This trend is expected to continue well into the foreseeable future as the rapidly burgeoning Internet of Things (IoT) ramps up. Perhaps not surprisingly, the exponential increase in data has created a number of new bottlenecks in data centers, prompting the industry to examine fresh approaches to system architecture.
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Smart Data Acceleration with FPGAs and DRAM
The proliferation of connected devices has significantly increased the amount of data being captured, moved and analyzed. This trend is expected to continue well into the foreseeable future as the rapidly burgeoning Internet of Things (IoT) ramps up. Perhaps not surprisingly, the exponential increase in data has created a number of new bottlenecks in data centers, prompting the industry to examine fresh approaches to system architecture.
Currently, data centers aggregate numerous individual servers into a pool of processing units. Large, data-intensive tasks are distributed across multiple racks of servers. However, this one size fits all approach, typically characterized by a relatively fixed amount of compute, memory, storage and I/O resources in each server, frequently leads to an acute under-utilization of resources. This is because specific tasks may require a tailored amount of each compute resource in real-time. Simply put, the legacy server architecture contributes to low CPU utilization rates, high latencies to access data, reduced power efficiency and increased TCO.
According to Steven Woo, VP of Systems and Solutions at Rambus, two of the most important issues facing systems today are the impact of moving data over long distances to CPUs, and the inherent difficulty of optimizing the performance and power efficiency of data processing.
“This is why we launched our Smart Data Acceleration (SDA) Research Program. We want to address these and other issues by rethinking how systems should be architected in the future,” Woo told Rambus Press during a recent interview in Sunnyvale. “As part of this program, we’ve created the SDA engine – which pairs an FPGA with large capacities of DRAM.”
Essentially, says Woo, the FPGA provides flexible acceleration and offload capabilities, while the platform’s significant memory capacity enables low latency access to large amounts of data. Coupling the FPGA with high memory capacity minimizes data movement by bringing processing resources to the data, allowing applications to benefit effectively from near data processing.
As Woo confirms, the SDA program is currently focused on optimizing the performance and power efficiency of data-intensive workloads for servers and data centers.
“The HPC community – in particular – has identified a number of challenges related to accelerating performance and improving power efficiency. Initiatives to address these issues include the Exascale Computing Project, FastForward and DesignForward,” he said. “With a focus on dramatic improvements in these critical metrics, increasing emphasis is being placed on memory and storage hierarchies to optimize future systems for evolving workloads and tasks. Of course, such improvements will ultimately benefit standard data center workloads as well.”
Woo describes the FPGA and software architecture of the SDA engine as a flexible environment that allows engineers to experiment with near data processing while exploring the interaction between application software, drivers, firmware, FPGA bitfiles and memory. The software layer enables the SDA engine to present itself to the rest of the system in various configurations, including as an ultra-fast solid-state disk, a Key-Value store and a large pool of memory.
“This means the SDA engine can be used across a wide range of applications that require high memory capacity, including transaction processing, in-memory databases, financial services, real-time analytics and risk analysis, imaging and transcoding,” Woo continued. “The versatility of the SDA platform also facilitates a continuum of integration strategies that balance ease of integration with performance improvement.”
For example, says Woo, acting as an ultra-fast solid-state disk, the SDA engine can integrate with existing systems in a matter of minutes by simply loading a driver and mounting the device. Applications can also be modified to take full advantage of the acceleration and offload capabilities of the SDA engine to achieve higher performance gains.
“Testing of the SDA platform configured as an ultra-fast solid state disk confirms higher IOPS rates at much lower latencies – with significantly better latency under load – compared to state-of-the-art Enterprise NVMe SSDs,” Woo concluded. “Across a range of 4KB workloads, the SDA engine can deliver 1M IOPS at latencies of 30 μs. Coupled with PCIe-based switches, multiple SDA engines can work together to provide scalable performance in a compact form factor.”
Interested in learning more about our SDA platform? You can check out our research program page here.
Protecting avionic systems from side-channel attack
Asaf Ashkenazi, a senior director of product marketing at Rambus’ security division, recently sat down with Neil Tyler of NewElectronics to discuss the potential threat side-channel attacks pose to avionic systems.
As Tyler points out, encryption is typically used to protect aerospace platforms. Although it is difficult to break the cryptographic algorithm itself, devices can readily reveal information during routine operations from such factors as power consumption, heat dissipation, time of computation and electromagnetic leaks.
“This type of [data] is referred to as side-channel information. The attacker can use this to determine the keys and break the cryptosystem. It’s breaking the system by going through the back door, [with attacks such as differential power analysis, or DPA],” he told the publication. “[In a broader sense], the threat of DPA attacks is on the rise and [aerospace] companies will need security solutions to safeguard high-value data. [This is why] Boeing recently signed a license agreement with Rambus for the inclusion of advanced DPA countermeasures in its products.”
According to Ashkenazi, electronic circuits are inherently leaky, as they produce a variety of emissions as by products that make it possible for an attacker to deduce how the circuit works and what data it is processing.
“All of these types of [side-channel] attacks can be recorded and reveal a surprising amount of information, especially if these attacks are combined,” he explained. “[Nor] do hackers need expensive equipment to do this. Pay a visit to the Dark Net and you can download the necessary software to carry out these attacks.”
As noted above, a wide range of DPA countermeasures are available to protect against various types of side-channel attacks, including special shielding, powering line condition and filtering, as well as blinding, which randomly adds a delay to any cryptographic computation.
“We have developed a technology that ensures signals emitted from any cryptographic operation are unreadable; any information generated will not make sense,” he added. “Essentially, we are hiding the data and, while the standard algorithm stays the same, the way in which it is implemented is changed.”
As we’ve previously discussed on Rambus Press, concerns about DPA attacks originated in the smart card market, although such attacks have since spread into other segments, including aerospace and defense. Fortunately, government and military systems can be protected from cyber adversaries with a hardware-centric security approach, which helps prevent the threat of reverse engineering and exploitation.
To evaluate vulnerability and resistance to side-channel attacks, Rambus has also developed a DPA Workstation (DPAWS) platform for its customers and partners. Essentially, DPAWS analyzes hardware and software cryptographic implementations for vulnerabilities to power and electromagnetic side-channel attacks. Specifically, DPAWS enables users to quickly assess any vulnerability that an FPGA, ASIC, CPU or microcontroller may have to side-channel analysis.
In addition, DPAWS includes an integrated suite of hardware and data visualization software to aid in the identification and understanding of vulnerabilities in cryptographic chips.
Interested in learning more? The full text of “Side Channel Attacks” by Neil Tyler is available on NewElectronics here (PDF). You can also check out our DPA Countermeasures product page here and our DPA Workstation product page here.
ChipEstimate and Rambus look beyond DDR4
Frank Ferro, a senior director of product management at Rambus, has penned an article for ChipEstimate about the future of DRAM in the age of the IoT. According to Ferro, the semiconductor industry has traditionally relied on Dennard Scaling and Moore’s Law to ensure the creation of ever more advanced process nodes at a steady cadence.
“However, development costs at each advanced node continue to multiply as Moore’s Law begins to slow and Dennard Scaling fades into the distant past,” he explained.
ChipEstimate and Rambus look beyond DDR4
Frank Ferro, a senior director of product management at Rambus, has penned an article for ChipEstimate about the future of DRAM in the age of the IoT. According to Ferro, the semiconductor industry has traditionally relied on Dennard Scaling and Moore’s Law to ensure the creation of ever more advanced process nodes at a steady cadence.
“However, development costs at each advanced node continue to multiply as Moore’s Law begins to slow and Dennard Scaling fades into the distant past,” he explained.
“Consequently, many in the semiconductor industry are taking a closer look at the advantages of refining the silicon design process at an architectural level, rather than relying primarily on process geometries to solve thorny problems.”
For example, says Ferro, there are a number of distinct physical design challenges associated with architecting higher bandwidth memory and faster PHYs that can no longer be addressed by advanced process nodes alone.
“Indeed, the current generation of DDR4 memory deployed in datacenters runs at 2.4Gbps. The maximum speed grade – 3.2Gbps – is expected to start shipping later this year (2016),” he continued. “Perhaps not surprisingly, achieving a top speed of 3.2Gbps has introduced a number of challenges for both SoC and system designers. More specifically, as memory speeds exceed 2.4Gbps, precise signal integrity analysis of the memory channel is required. This is why there are only a handful of companies with working 3.2Gbps prototype hardware capable of supporting real-world server requirements.”
Over the next five years, says Ferro, server memory will likely demand a 33% increase in bandwidth capability per year to keep pace with processor improvements and avoid serious system bottlenecks. Simply put, DRAM of all variants will have to achieve speeds of over 12Gbps by 2020 for optimal performance.
“Although this figure represents a 4X performance increase over the current DDR4 standard, Rambus Beyond DDR4 silicon has demonstrated that even traditional DRAM signaling still has ample headroom for growth. Such speeds, within reasonable power envelopes, are indeed possible,” Ferro explained. “For example, Rambus’ Beyond DDR4 demo silicon offers a 25% improvement in power efficiency while hitting data transfer rates up to 6.4Gbps in a multi-rank, multi-DIMM configuration. This means the memory interface is three times faster than current DIMMs topping out at 2.133Gbps – and two times the maximum speed specified for DDR4 at 3.2Gbps.”
The 25% power savings, says Ferro, can be attributed to several factors. Firstly, the low-swing signaling reduces the I/O power required on the interface. This design is also ‘asymmetric,’ meaning that complex timing and the equalization circuits are all implemented in the PHY, thus greatly simplifying the DRAM interface and reducing cost. Removing complex timing circuits such as PLLs and DLLs from the DRAM makes it extremely agile, facilitating the rapid entrance and exit from power down mode. Because the memory controller is the originator of all memory requests, it is capable of implementing an aggressive and granular DRAM power management scheme.
Interested in learning more? The full text of “Looking Beyond DDR4 in the Age of the IoT” by Frank Ferro can be read on ChipEstimate here, while our Beyond DDR4 page is available here.
Rambus Signs License Agreement with Idaho Scientific
DPA countermeasures to strengthen the security of Idaho Scientific anti-tamper solutions
SUNNYVALE, Calif. – August 9, 2016 – Rambus Inc. (NASDAQ:RMBS) today announced it has signed an agreement with Idaho Scientific, LLC to license its Differential Power Analysis (DPA) countermeasures for use in Idaho Scientific’s security IP Cores for FPGAs and defense ASICs. Through this agreement, Idaho Scientific’s customers, which include many of the world’s largest defense contractors, will gain access to advanced DPA countermeasures, safeguarding the data integrity of applications requiring a high level of security.
“By incorporating Rambus’ technology into our IP cores, we provide our customers access to premier solutions that are immune to DPA attacks,” said Dale Reese, president of Idaho Scientific. “The Rambus DPA countermeasures enhance the efficiencies of our FPGA and ASIC encryption cores, which are especially critical to our aerospace and defense customers.”
DPA countermeasures, developed by Rambus Cryptography Research, consist of a broad range of software, hardware, and protocol techniques that protect devices from side-channel attacks. DPA is a type of side-channel attack that monitors variations in the electrical power consumption or electro-magnetic emissions from a target device. These measurements can then be used to obtain cryptographic keys and other sensitive information from semiconductors.
“Today’s leading aerospace and defense companies are looking for solutions to counter the increasing threat of side-channel attacks,” said Dr. Martin Scott, general manager of the Rambus Security Division. “Broader and faster adoption of DPA countermeasures in the FPGA ecosystem will ensure that components are insulated from these types of vulnerabilities. Idaho Scientific has the ability to rapidly deliver solutions based on our DPA countermeasures that will bring significant benefits to the industries they serve, where safety and security are a top priority.”
About Rambus Security Division
The Rambus Security Division is dedicated to providing a secure foundation for a connected world. Integrating technologies from Cryptography Research, Bell ID and Ecebs, our innovative solutions span areas including tamper resistance, content and media protection, network security, mobile payment, smart ticketing, and trusted transaction services. Our technologies protect nearly nine billion licensed products annually, providing secure access to data and creating an economy of digital trust between our customers and their customer base. Additional information is available at rambus.com/security.
About Rambus Inc.
Rambus creates cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting. Our chips, customizable IP cores, architecture licenses, tools, services, software, training and innovations improve the competitive advantage of our customers. We collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation labs. Our products are integrated into tens of billions of devices and systems, powering and securing diverse applications, including Big Data, Internet of Things (IoT), mobile, consumer and media platforms. At Rambus, we are makers of better. For more information, visit rambus.com.
About Idaho Scientific, LLC.
Idaho Scientific is a provider of security, cryptography, and anti-tamper IP cores to many of the world’s largest defense contractors. The threats facing our nations tactical and critical infrastructure evolve rapidly. To combat these threats, Idaho Scientific’s maintains cutting edge research through internal and government sponsored programs. The technologies developed under these efforts are matured, tested, and deployed within our nation’s most critical systems. In addition to IP offerings, Idaho Scientific provides anti-tamper and cyber security engineering services. As subject matter experts, Idaho Scientific works with customers to evaluate system vulnerabilities, design countermeasures, and deploy solutions. For more information, visit www.idahoscientific.com.
