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CRYPT-IP-120 / EIP-120 AES Crypto, SHA-2 Hash Core with DMA

CRYPT-IP-120 (EIP-120) is IP for combining local key storage, AES cipher (AES-IP-39), SHA-2 hash (HASH-IP-57) and DMA capability. Designed for fast integration, low gate count and full transforms, the CRYPT-IP-120 DMA crypto engine provides a reliable and cost-effective embedded IP solution that is easy to integrate into high speed processing pipelines.

AES Crypto, SHA-2 Hash Core with DMA

Up to 1Gbps @500MHz


How the CRYPT-IP-120 works

By using dedicated hardware accelerators, the CRYPT-IP-120 provides a first performance boost compared to software execution on the host processor. The second advantage is the ability to store keys in an integrated RAM via DMA, and keep these inaccessible but usable for the host/application.

The CRYPT-IP-120 DMA crypto core provides hardware cryptographic algorithm implementations for optimal performance, user experience, battery lifetime and robust security.

Due to the flexibility of the CRYPT-IP-120 architecture, other configurations, such as 3G/LTE specific versions are available on request. These can include SNOW3G Kasumi, AES-XTS but also other Inside Secure basic IP modules.

CRYPT-IP-120 Information

Key benefits:

  • Silicon-proven implementation
  • Fast and easy to integrate into SoCs
  • Flexible layered design
  • Complete range of configurations
  • World-class technical support

All configurations:

  • DMA controller
  • AHB master and AHB slave interface


  • Local key Store
  • AES with all key sizes and modes (details below)
  • Gate count: 49-53k gates, depending on CMOS nodes


  • SHA-256 / SHA-224
  • Gate count: gates, depending on CMOS nodes


  • SHA-256 / SHA-224 / SHA-512 / SHA-384
  • Gate count: gates, depending on CMOS nodes


  • HMAC
  • MAC key processing (HMAC)
  • SHA-256 / SHA-224 / SHA-512 / SHA-384
  • Gate count: gates, depending on CMOS nodes


  • AES with all key sizes and modes (details below)
  • Local key store
  • SHA-256 / SHA-224
  • Gate count: 74-79k gates, depending on CMOS nodes

Control interface:

  • Simple register based control interface
  • Operation done interrupt
  • DMA done interrupt

Crypto algorithm (AES) (CRYPT-IP-120b and CRYPT-IP-120f)

  • 128, 192 and 256-bit key support
  • AES-GCM (Optional, by default available)
  • Internal GCM hash key calculation
  • Key load via the Key Store only
  • IV writing and reading via slave interface
  • Data load via the slave and DMA
  • Data readout via the slave and DMA
  • Tag readout via the slave and DMA

Hash algorithm (CRYPT-IP-120f, CRYPT-IP-120c, CRYPT-IP-120d)

  • SHA-256 / SHA-224
  • SHA-512 / SHA-384

(CRYPT-IP-120c-h and CRYPT-IP-120d-h configuration)

  • Basic hash
  • HMAC (using several basic hash operations)
  • Digest and length load via the slave
  • Data load via the slave and DMA
  • Digest readout via the slave and DMA

Key store (CRYPT-IP-120b and CRYPT-IP-120f configuration)

  • Secure management of sensitive security parameters
  • Local 8 x 128-bit (or 4 x 192-bit/256-bit) encryption key storage
  • Writable via DMA only

DMA controller

  • Two channels (inbound, outbound)
  • 16-bit DMA length

AHB interface (AMBA V2.0)

  • 32-bit AHB slave interface for configuration and data
  • 32-bit AHB master interface for keys, crypto and hash blocks
  • Optional use of privileged accesses for key reads

AXI interface (AMBA V3.0)

  • 32-bit and 64-bit AXI master and slave interface available on request

Embedded memory

  • Key store RAM: 32×32 bit 1 port RAM

Performance @ 500MHz

  • 1 Gbps AES-128 & -192
  • 0.8Gbps AES-256
  • 4Gbps SHA-256
Introduction to Side-Channel Attacks eBook

Introduction to Side-Channel Attacks

Side-channel attacks conducted against electronic gear are relatively simple and inexpensive to execute. Such attacks include simple power analysis (SPA) and Differential Power Analysis (DPA). As all physical electronic systems routinely leak information, effective side-channel countermeasures should be implemented at the design stage to ensure protection of sensitive keys and data.

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