Home > Security IP > Inline Memory Encryption IP
Rambus inline memory encryption and inline cipher engines protect data in use including applications for secure memory transactions between hosts and attached memory at high throughput with low latency. Differential Power Analysis (DPA) protection and Data Path Integrity is available as an option on most solutions as a counter to DPA and related side-channel attacks.
| Solution | Product Brief | Description |
|---|---|---|
| IME-IP-341 | Inline memory encryption engine for ASIC SoCs. AES-XTS and SM4-XTS encryption, decryption and integrity. DPA protection option. Channelized with 128-bit AXI4 master/slave interface. Includes native key management. | |
| IME-IP-340 | Inline memory encryption engine, for FPGA. AES-GCM mode. DPA protection option. Channelized with 128-bit AXI master/slave interface. Includes memory manager, last level cache and native key management. | |
| ICE-IP-339 | Inline cipher engine with AXI, for memory encryption. AES-XTS/GCM, SM4-XTS/GCM. DPA protection option. Channelized with 128-bit AXI master/slave interface. | |
| ICE-IP-338 | Inline cipher engine, for memory encryption. AES-XTS/GCM, SM4-XTS/GCM. DPA protection option. Channelized with inline native interface. | |
| ICE-IP-63 | Inline cipher engine for PCIe, CXL, NVMe, 5G FlexE link integrity and data encryption (IDE) using AES GCM mode. Channelized with inline native interface. |
AI’s fast evolution is producing autonomous systems that can operate with minimal human oversight, improve themselves and become effective at decision-making in complex environments. These developments require careful consideration of security and privacy. To limit the overhead performance impact (area, throughput, latency and power), hardware-based security solutions can be deployed using state-of-the-art silicon IP.
