Protocol aware IPsec/TLS/MACsec/DTLS packet engine with look-aside interface for multi-core application processors
2000Mbps, programmable, supports new and legacy crypto algorithms, AMBA interface
Supported by Driver development kit, QuickSec IPsec toolkit
TThe EIP-97 Multi-Protocol Engine is a protocol aware packet engine IP with a look-aside bus interface and a packet transform engine. The Multi-Protocol engine is used as a bus master in the data plane of the system and processes packets with very little CPU intervention. This engine supports an AMBA (AXI, AHB, TCM) or a PLB SoC bus interface and can be delivered in different configurations to support IPsec as well as SSL/TLS. Compared to the Protocol-IP-93 it offers higher performance, more algorithms, protocol flexibility through token instructions and supports multi-core CPUs.
The EIP-97 is designed to off-load the host processor to improve the speed of protocol operations and reduce power in gigabit application processors for: VPN routers; home media gateways; IoT gateways; femtocells, VPN appliances; surveillance cameras; and FTTH routers.
Performance for large packet sizes is 2000 Mbps for any supported protocol. IPsec performance for small packet sizes is 1000 Mbps. System clock speed is 500 MHz. Gate count is between 400 and 600k gates depending on the configuration.
Driver Development Kit.IPsec (IPv4 and IPv6):
SSL3.0 / TLS1.0 / TSL1.1 / TLS1.2 / DTLS1.0 / DTLS1.2:
SRTP packet transforms according to RFC3711:
The cryptographic engine supports the following cryptographic algorithms:
The Hash engine supports the following algorithms:
The Pseudo Random Number Generator supports:
The DMA controller supports:
Master and slave interface:
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