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Below is an archive of Rambus videos.

Ask the Experts: PCIe 7 Switch with TDM

Video: How PCIe 7.0 Switches and Time Division Multiplexing Enable Scalable AI Systems

As AI infrastructure grows from hundreds to thousands of accelerators, connectivity has become just as important as compute and memory. In this Ask the Experts video, Lou Ternullo, Sr. Director of Product Management for Interconnect IP at Rambus, explains how PCIe 7.0 switch IP and Time Division Multiplexing (TDM) help solve the bandwidth, scalability, and flexibility challenges of next-generation AI architectures.

Watch the video to learn how PCIe 7 switching enables efficient communication between GPUs, SmartNICs, SuperNICs, storage, and memory resources in large-scale AI deployments.

What This Video Covers

In this Ask the Experts, Rambus explores:

  • Why connectivity has become critical for AI infrastructure
  • How PCIe 7.0 increases bandwidth to support next-generation workloads
  • Why PCIe switches are essential for scalable and disaggregated architectures
  • The role of SmartNICs and SuperNICs in modern data centers
  • How Time Division Multiplexing (TDM) improves bandwidth utilization
  • Why Rambus PCIe 7 switch IP is optimized for complex AI networking SoCs

Why Connectivity Matters in AI Infrastructure

As AI systems continue to scale, adding more accelerators alone is not enough. GPUs, SmartNICs, storage devices, memory expanders, and networking resources must communicate efficiently across increasingly complex system architectures.
While AI discussions often focus on compute and memory, the interconnect fabric plays an equally important role. If data cannot move quickly between resources, overall system performance suffers regardless of how powerful the underlying processors may be.

What Is New in PCIe 7.0?

The headline advancement in PCIe 7.0 is the doubling of bandwidth to 128 GT/s, delivering significantly higher throughput for AI training, inferencing, and large-scale data movement.

However, increasing data rates introduces new challenges, including:

  • Signal integrity at extreme speeds
  • Power consumption optimization
  • Efficient bandwidth sharing across many devices
  • Scalable connectivity architectures

As systems become larger and more distributed, efficiently utilizing available bandwidth becomes just as important as increasing raw bandwidth.

Why PCIe Switches are Essential for AI Systems

In large AI deployments, direct connections between every device are impractical. PCIe switches enable multiple devices to communicate efficiently through a shared fabric.

PCIe switches provide:

  • High-density connectivity
  • Flexible system design
  • Support for composable infrastructure
  • Resource sharing across accelerators, storage, and networking devices

They are a foundational technology for modern scale-up and scale-out AI architectures.

Where are PCIe Switches Used?

According to Rambus, PCIe 6.0 and PCIe 7.0 switches are increasingly being implemented in advanced networking devices such as SmartNICs and SuperNICs.

These devices sit at the intersection of:

  • Compute
  • Networking
  • Storage
  • AI acceleration

Their role is to efficiently move data between CPUs, GPUs, accelerators, storage subsystems, and the network.

What is a SmartNIC?

A SmartNIC (Smart Network Interface Card) extends traditional network functionality by offloading infrastructure services from the CPU. Instead of simply moving packets, SmartNICs can handle:

  • Network virtualization
  • Security processing
  • Storage acceleration
  • Telemetry and monitoring

By offloading these functions, SmartNICs free CPU resources for application workloads, improving efficiency in cloud and hyperscale environments.

What is a SuperNIC?

A SuperNIC is an advanced evolution of the SmartNIC designed specifically for AI and accelerated computing environments.

Unlike traditional SmartNICs, SuperNICs focus on enabling communication across large clusters of GPUs and accelerators by providing:

  • Extreme data movement capabilities
  • High-radix connectivity
  • Integration with accelerator fabrics
  • Support for tightly synchronized AI workloads

These capabilities are critical for AI training environments that rely on efficient communication among thousands of GPUs.

What Is Time Division Multiplexing (TDM)?

Time Division Multiplexing (TDM) is a technique that dynamically allocates bandwidth among connected endpoints using time slots rather than dedicating fixed bandwidth to each device.

For PCIe switching, TDM provides several advantages:

  • Dynamic bandwidth allocation based on demand
  • Improved link utilization
  • More efficient sharing of switch resources
  • Greater flexibility in system configuration

TDM also allows system designers to configure PCIe lane groupings in multiple ways, such as:

  • 1 × 16
  • 2 × 8
  • 4 × 4

This flexibility enables a single switch architecture to support different combinations of GPUs, SSDs, and other endpoint devices.

Why Is TDM Important for AI Workloads?

AI workloads rarely generate consistent traffic patterns. Different accelerators, storage devices, and memory resources may require dramatically different bandwidth levels over time.

TDM helps by:

  • Allocating bandwidth where it is needed most
  • Reducing wasted bandwidth
  • Improving overall utilization
  • Allowing systems to scale more efficiently

This dynamic approach helps maintain high performance without excessive overprovisioning.

How TDM Improves PCIe 7.0 Performance

At PCIe 7.0 speeds, inefficiencies become increasingly costly. Underutilized links and bandwidth contention can significantly impact overall system performance.

TDM helps address these challenges by:

  • Optimizing bandwidth allocation
  • Reducing bottlenecks
  • Managing traffic more predictably
  • Supporting deterministic system behavior

For large AI systems, predictability and efficiency are essential for maintaining performance at scale.

Rambus PCIe 7 Switch IP with TDM

Rambus offers advanced PCIe 7 switch IP with integrated TDM capabilities for AI networking SoCs, including those used in SmartNIC and SuperNIC designs.

Key capabilities include:

  • PCIe 7.0 support at 128 GT/s
  • Advanced switching architectures
  • Integrated TDM functionality
  • Optimization for AI networking applications
  • Physically aware implementation for large SoCs

The architecture is designed to address the routing, latency, and implementation challenges associated with large, high-performance networking devices.

Why Choose Rambus for PCIe 7 Switch IP?

Rambus brings decades of expertise in:

  • High-speed interface design
  • Signal integrity
  • PCIe technology
  • Complex SoC implementation

The company’s approach focuses on real-world deployment challenges, enabling customers to implement highly scalable PCIe switching solutions for AI infrastructure.

Watch the Ask the Experts Video

Learn how PCIe 7.0 switch IP and Time Division Multiplexing help eliminate connectivity bottlenecks and enable scalable AI infrastructure.

Frequently Asked Questions about PCIe 7.0

What is PCI Express 7.0?
PCIe 7.0 is the seventh generation of the PCI Express specification, doubling data rates to 128 GT/s to support AI, accelerated computing, and disaggregated system architectures.

Why are PCIe switches important for AI systems?
PCIe switches enable efficient communication among GPUs, storage, networking resources, and accelerators, making large-scale AI infrastructures possible.

How do SmartNICs and SuperNICs differ?
SmartNICs primarily offload infrastructure functions from CPUs, while SuperNICs are optimized for large-scale AI environments that require communication among thousands of accelerators.

What does Rambus provide for PCIe 7 switching?
Rambus offers PCIe 7 switch IP with TDM support, designed for AI networking SoCs, SmartNICs, and SuperNICs.

Ask the Experts: SOCAMM2 Server Memory Module Chipsets

Video: How SOCAMM2 Brings LPDDR Power Efficiency to Scalable AI Server Memory

As AI models grow larger and more power hungry, memory is emerging as a key limiter in AI server design. In this Ask the Experts video, Piero Bianco, Senior Director of Product Marketing for Power Management ICs at Rambus, explains how SOCAMM2 addresses the power, scalability, and serviceability challenges of modern AI servers.

Watch the video to learn how SOCAMM2 combines the bandwidth and power efficiency of LPDDR5X with the modularity and reliability required in data center environments.

What This Video Covers

In this Ask the Experts session, Rambus explores how SOCAMM2 enables next‑generation AI servers, including:

  • Why memory power consumption is becoming a limiting factor for AI scaling
  • How LPDDR differs from traditional DDR memory in AI workloads
  • The challenges of soldered LPDDR in data center environments
  • What SOCAMM2 is and how it works
  • Key benefits of SOCAMM2 for AI server designers
  • What Rambus provides in its SOCAMM2 server module chipset

Why Memory Power Matters for AI

The AI industry has made enormous advances in compute, GPUs, and accelerators. Today, power consumption is increasingly the limiting factor in scaling AI systems.

AI models require memory not only for capacity, but for constant, high‑bandwidth data movement. Moving weights, activations, and key‑value caches consumes significant energy. As models grow, memory power efficiency becomes as important as compute performance.

Why LPDDR Is Attractive for AI Workloads

LPDDR was originally designed for mobile devices, but its characteristics align well with AI requirements:

  • High bandwidth
  • Low signaling voltage
  • Lower power consumption per bit transferred

For AI workloads that prioritize bandwidth and energy efficiency over ultra‑low latency, LPDDR offers clear advantages. However, LPDDR was designed to be soldered close to the processor, which creates challenges in server environments.

The Limitations of Soldered LPDDR in Servers

Using soldered LPDDR in AI servers introduces several operational challenges:

  • Repairability: If a memory device fails, the entire board must be replaced
  • Supply chain rigidity: Memory configuration is fixed at manufacturing time
  • Lack of upgradability: Capacity cannot be expanded over the system’s lifetime
  • Service costs: Repairs require more downtime and labor

These limitations reduce flexibility and increase total cost of ownership in data centers.

What Is SOCAMM2?

SOCAMM2 stands for Small Outline Compression Attached Memory Module. It is a JEDEC‑defined memory standard that uses LPDDR5X packaged into a compact, server‑grade module.

Instead of soldering LPDDR directly onto the board, SOCAMM2 places LPDDR memory on a removable module. The module is designed to preserve LPDDR’s low‑voltage signaling and power efficiency while enabling modularity and serviceability.

SOCAMM2 modules sit flat on the motherboard, maximizing signal integrity and supporting the physical and electrical constraints of AI server designs.

Key Benefits of SOCAMM2 for AI Servers

SOCAMM2 delivers a combination of benefits tailored to AI infrastructure:

High Bandwidth with Low Power
SOCAMM2 preserves LPDDR’s core advantages, delivering high bandwidth at significantly lower power consumption compared to traditional server memory.

Modularity and Serviceability
Failed memory modules can be replaced without swapping entire boards, reducing downtime and maintenance cost.

Scalability
SOCAMM2 allows memory to be placed farther from the CPU while maintaining signal integrity, enabling higher memory capacity configurations around AI processors.

Improved Cooling Options
The flat, compression‑attached form factor creates more spacing for airflow and liquid cooling, which is critical for high‑power AI systems.

Industry Standardization
As a JEDEC standard, SOCAMM2 enables multi‑vendor sourcing and avoids proprietary lock‑in for system designers and operators.

What Rambus Provides for SOCAMM2

Rambus offers a complete SOCAMM2 server module chipset, designed to support enterprise‑grade AI deployments.

The Rambus SOCAMM2 chipset includes:

  • High‑efficiency on‑module power management ICs
  • Multiple voltage regulators optimized for LPDDR5X
  • An SPD hub supporting configuration, presence detection, and telemetry
  • Integrated temperature sensing for monitoring and reliability

Together, these components enable robust, energy‑efficient SOCAMM2 module designs.

Why Choose Rambus for SOCAMM2 Chipsets?

Rambus brings decades of experience in high‑speed memory interfaces and system‑level design. Its deep expertise spans signal integrity, power conversion, noise reduction, and compact form factor memory systems.
By working closely with CPU vendors, memory suppliers, and system OEMs, Rambus helps customers deliver SOCAMM2 solutions with high reliability, efficient power delivery, and scalable performance for AI servers.

Frequently Asked Questions about SOCAMM2

What is SOCAMM2?
SOCAMM2 is a JEDEC‑standard memory module that packages LPDDR5X into a removable, server‑grade form factor for AI systems.

Why is SOCAMM2 important for AI servers?
It combines LPDDR’s power efficiency and bandwidth with the modularity, scalability, and serviceability required in data centers.

How is SOCAMM2 different from soldered LPDDR?
SOCAMM2 enables memory replacement, upgradeability, and better supply chain flexibility compared to soldered LPDDR designs.

What does Rambus supply for SOCAMM2?
Rambus provides a complete SOCAMM2 chipset including power management ICs and an SPD hub with telemetry support.

Ask the Experts: MACsec at Terabit Line Rates

In this episode of Ask the Experts, we chat with Maxim Demchenko about MACsec at Terabit Line Rates. In this episode, we cover:

  • Why was MACsec was developed
  • How MACsec has evolved from point-to-point layer 2 security
  • MACsec applications
  • The new Rambus MACsec-IP-164

Ask the Experts: Client Memory Module Chipsets

Video: How AI Is Reshaping Client Memory, LPCAMM2, and DDR5 Client DIMMs
As AI workloads move from the cloud to the PC, client computing architectures are undergoing a major transformation. In this Ask the Experts video, Carlos Weissenberg, Vice President in Rambus’ Memory Interface Chip business, explains how AI is driving new memory requirements and why next‑generation client memory chipsets are critical to meeting those demands.

Watch the video to learn how AI PCs, LPCAMM2, and new DDR5 client DIMM formats are redefining performance, power efficiency, and system flexibility.

Video: How AI Is Reshaping Client Memory, LPCAMM2, and DDR5 Client DIMMs
As AI workloads move from the cloud to the PC, client computing architectures are undergoing a major transformation. In this Ask the Experts video, Carlos Weissenberg, Vice President in Rambus’ Memory Interface Chip business, explains how AI is driving new memory requirements and why next‑generation client memory chipsets are critical to meeting those demands.

Watch the video to learn how AI PCs, LPCAMM2, and new DDR5 client DIMM formats are redefining performance, power efficiency, and system flexibility.

What This Video Covers

In this Ask the Experts episode, Rambus explores the key trends shaping modern client computing, including:

  • How AI is driving a renaissance in the PC market
  • Why client systems need higher memory bandwidth and capacity
  • What LPCAMM2 is and why it matters for thin and light notebooks
  • The transition from UDIMMs and SODIMMs to CUDIMMs and CSODIMMs
  • How client clock drivers enable DDR5 speeds beyond 6400 MT/s
    Rambus client memory chipset solutions and differentiation

How AI Is Changing the Client Computing Architecture

AI is fundamentally changing what users expect from PCs. Next‑generation systems are being designed as AI PCs, with dedicated hardware optimized for local AI inferencing.

Running AI models directly on a PC requires:

  • Higher memory bandwidth
  • Greater memory capacity
  • Low latency access to large, local models

As AI models and use cases continue to evolve, these requirements are driving new memory architectures and module designs for both desktop and notebook PCs.

What Is LPCAMM2?

LPCAMM2 is a JEDEC‑standard memory module that enables the use of LPDDR memory in notebook PCs while maintaining the flexibility of a removable module. LPDDR offers:

  • Higher data rates
  • Lower power consumption
  • Improved signal integrity due to proximity to the processor

Historically, LPDDR was soldered directly to the motherboard, locking in memory capacity and limiting repairability or upgrades. LPCAMM2 overcomes these limitations by delivering LPDDR performance in a compact, low‑profile module that supports memory expansion and serviceability.

Key Benefits of LPCAMM2 for Notebooks
LPCAMM2 combines the advantages of LPDDR with the flexibility of modular memory, including:

  • Support for ultra‑thin notebook designs
  • Lower power consumption compared to DDR5
  • High bandwidth for AI workloads
  • Improved signal integrity
  • Upgrade and repair capability not possible with soldered memory

This makes LPCAMM2 an ideal solution for next‑generation AI notebooks that demand both performance and efficiency.

The Evolution of DDR5 Client Memory Modules
At DDR5 speeds of 6400 MT/s and above, traditional client memory architectures begin to face signal integrity and timing challenges.

As a result, client platforms are transitioning to new DIMM formats:

  • CUDIMMs for desktop PCs
  • CSODIMMs for notebook PCs

These modules integrate a client clock driver (CKD), which improves signal integrity and enables higher memory bandwidth at advanced data rates.

Why Client Clock Drivers Matter

Client clock drivers help DDR5 client systems scale to higher speeds by:

  • Improving clock signal quality
  • Reducing jitter at high frequencies
  • Enabling reliable operation beyond 6400 MT/s

Together with advanced power management and SPD hub components, clock drivers are a key enabler for next‑generation DDR5 client memory performance.

Rambus Client Memory Chipset Solutions

Rambus offers a complete portfolio of client memory interface chipsets designed to support emerging memory form factors and higher data rates. These solutions include:

  • Client clock drivers for CUDIMMs and CSODIMMs
  • Power management ICs optimized for DDR5 client modules
  • Dedicated PMICs for LPCAMM2 and LPDDR memory
  • SPD hub devices for client memory modules

This integrated approach enables system and module manufacturers to more easily adopt new memory standards and bring high‑performance client platforms to market.

Why Choose Rambus for Client Memory Chipsets?

Rambus brings over 30 years of memory subsystem innovation, spanning both server and client platforms. With deep expertise in signal integrity, power management, and high‑volume semiconductor production, Rambus helps customers navigate each new memory transition with confidence.
As AI increases the computational demands on client PCs, Rambus solutions are designed to ensure scalable performance, efficiency, and reliability.

Watch the Ask the Experts Video
Learn how AI is driving new memory requirements and how Rambus client memory chipsets enable next‑generation PCs.

Frequently Asked Questions

What is an AI PC?
An AI PC is a client system designed with dedicated hardware to run AI inferencing workloads locally, requiring higher memory bandwidth and capacity.

What is LPCAMM2?
LPCAMM2 is a JEDEC‑standard memory module that brings LPDDR performance to notebooks while allowing upgrades and repairs.

Why are CUDIMMs and CSODIMMs needed for DDR5?
At higher DDR5 speeds, client clock drivers are required to maintain signal integrity and enable reliable operation beyond 6400 MT/s.

What does Rambus provide for client memory systems?
Rambus provides complete client memory chipsets, including clock drivers, PMICs, and SPD hubs, supporting both DDR5 and LPCAMM2.

Ask the Experts: CryptoManager Root of Trust

On this episode of Ask the Experts, we chat with Parvez Shaik about the latest developments in security and the concept of the root of trust. Watch this video to learn about the importance of addressing supply chain vulnerabilities, the advantages of a hardware root of trust, and the new features of the third-generation CryptoManager Root of Trust products.

Key Topics in this episode:

  • What is the current threat environment faced by chip and system makers?
    What is a root of trust and its role in security?
    What are the advantages of implementing a root of trust in hardware?
    What’s new in the third-generation CryptoManager Root of Trust?

Ask the Experts: The State of AI

Hear from Rambus Expert Steven Woo about the latest developments in AI and the implications for hardware and computing architecture. Learn about chain-of-thought and the innovations needed to support its computational demands.

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