In this video, we demonstrate the Rambus Controller IP for CXL 2.0 and the CXL.mem protocol used to access Host-managed Device Memory, or HDM. This demonstration is performed using Intel’s Pre-Production Xeon processor as a host, connected to an FPGA board, instantiating Rambus’ CXL Controller and CXL.mem test design.
SK hynix, Inc., Amkor Technology, eSilicon, Northwest Logic and Avery Design Systems have joined forces to offer a complete High Bandwidth Memory (HBM) supply chain solution. HBM is a JEDEC-defined standard that utilizes 2.5D technology to interconnect a SoC and a HBM memory stack.
To learn more about the Rambus HBM2E Controller, click here.
Rambus’, formerly Northwest Logic, CSI-2 Rx and DSI Host Controller Core MIPI demonstration with Inrevium FIDUS’s Meticom-based, dual-MIPI FMC Board running with a Xilinx Virtex-7 development board.
This demo consists of the following; A 13 megapixel Omnivision camera provides a MIPI output running 4 lanes of data at 1200 Mbit/s for each lane. The camera data goes into the Fidus/Invrevium MIPI D-PHY card. This card uses a Meticom chip to translate the MIPI signal into FPGA compatible signals. The data from the Meticom chip then goes into the Virtex-7 located on the development board. The Virtex-7 uses Northwest Logic’s CSI-2 Rx Controller Core to convert the data back into pixels. These pixel are bayer processed, gamma and color corrected, frame buffered and output to the HDMI display.
In addition, The Virtex-7 uses Northwest Logic’s DSI Host Controller to drive a color bar pattern through the Inrevium MIPI D-PHY card into a MIPI-compatible 10 inch display. This display has a 1920×1080 resolution. The MIPI signals from the DSI Host Controller core are running at 1000 Mbit/s on each of the 4 data lanes.
To learn more about Rambus MIPI Controllers, click here.
Made for high speed, reliability and power efficiency, our DDR3 and DDR4 chipsets, recently acquired from Inphi, for RDIMM and LRDIMM server modules deliver top-of-the-line performance and capacity for the next wave of enterprise and data center servers.
Learn more about Rambus’ server DIMM Chipsets here.
Rambus Senior Engineering Manager Arun Vaidyanath demonstrates the latest Rambus test chip running in 3 modes: high-speed differential, GDDR5, and DDR3. Groundbreaking memory technologies developed by Rambus enable signaling at 20 gigabits per second (Gbps) while maintaining best-in-class power efficiency, and up to 12.8 Gbps for single-ended signaling.