Sensors drive the algorithms that interpret the data enabling ADAS driving systems. High bandwidth global shutter cameras, and low-latency, low-power radar, lidar and sonar sensors’ streaming data leverage MIPI CSI-2® technologies to meet challenging design requirements. This session will discuss how highly configurable MIPI CSI-2 based PHY and Controller sub-system solutions can be tailored to address the needs of autonomous driving. Example customer use cases will illustrate the implementation of these MIPI CSI-2 solutions.
High-Performance Memory: Ask Me Anything
With high-performance memory experts covering architecture, chips and IP, we’re looking forward to your questions. Please join us for this Ask Me Anything session to get the latest on technology and trends for the world’s highest bandwidth memory solutions including DDR5, HBM3 and GDDR6.
High-Speed Interface Solutions for 5G
A rapid rise in the size and sophistication of inferencing models has necessitated increasingly powerful hardware deployed at the network edge and in the endpoint devices. To keep these inferencing processors and accelerators fed with data requires a state-of-the-art memory solution that delivers extremely high bandwidth. Frank Ferro will discuss the design and implementation considerations of GDDR6 memory subsystems to address the bandwidth needs of these next-generation inferencing engines (JESD/CIPRI).
LPDDR5 Delivers High Bandwidth for a Growing Range of Applications
Initially designed for mobile phones and laptops, the bandwidth and low power characteristics of LPDDR make it an increasingly attractive choice of memory for applications in IoT, automotive, edge computing and the data center. Fifth-generation LPDDR5 raises data rates to 6.4 Gbps and bandwidth to 25.6 GB/s for a x32 DRAM device. In this session, Rambus and its partners OpenFive and Avery Design Systems will discuss their high-performance, high-quality, configurable LPDDR5 solution.
Accelerating Data Interconnects with PCI Express™ 6.0 & 5.0 Interface IP
The latest generation of the PCI Express, PCIe™ 6.0, advances performance to 64 GT/s in support of advanced workloads and networking. In this presentation, interface technology expert, Arjun Bangre will discuss the changes implemented in PCI Express 6.0, such as PAM4 signaling and low-latency forward error correction (FEC). In addition, Arjun Bangre will contrast PCIe 6.0 and 5.0 and explain how Rambus can support the PCIe interface your next design requires.
GDDR6 Memory Enables High-Performance Inferencing
A rapid rise in the size and sophistication of inferencing models has necessitated increasingly powerful hardware deployed at the network edge and in the endpoint devices. To keep these inferencing processors and accelerators fed with data requires a state-of-the-art memory solution that delivers extremely high bandwidth. Frank Ferro will discuss the design and implementation considerations of GDDR6 memory subsystems to address the bandwidth needs of these next-generation inferencing engines.
