The DisplayPortTM Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPort 1.4 specification. Forward Error Correction is required to ensure glitch-free Display Stream Compression (DSC) bitstream transport.
VDC-M 1.2 Decoder Product Brief
The Rambus VESA VDC-M 1.2 Decoder IP Core implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 decoder to deliver visually lossless video compression. The decoder supports various usage models, including typical MIPI Display Serial Interface 2 (MIPI DSI-2) usage models.
VDC-M 1.2 Encoder Product Brief
The Rambus VESA VDC-M 1.2 Encoder IP Core implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 decoder to deliver visually lossless video compression. The decoder supports various usage models, including typical MIPI Display Serial Interface 2 (MIPI DSI-2) usage models.
VESA DSC 1.1 Encoder IP Core For Automotive Displays Product Brief
The Rambus VESA DSC 1.1 Encoder IP Core for automotive displays implements a fully compliant VESA DSC 1.1 encoder. It contains additional safety features to detect and report transient or permanent faults in order to meet the high level of safety required by automotive applications. The IP core is ASIL-B ready, as per the ISO 26262 standard.
VESA DSC 1.2b Encoder IP Core
The Rambus VESA® Display Stream Compression (DSC) encoder IP core deliver visually lossless video compression performance, enabling designers to handle the growing bandwidth requirements of cutting-edge displays with higher resolutions, faster refresh rates, and greater pixel depths.
VESA DSC 1.2b Decoder Product Brief
The Rambus VESA® Display Stream Compression (DSC) decoder IP core deliver visually lossless video compression performance, enabling designers to handle the growing bandwidth requirements of cutting-edge displays with higher resolutions, faster refresh rates, and greater pixel depths.
