The tutorial will focus on DRAM architecture, specifically looking at design tradeoffs and subsequent impact to the overall system performance, power, cost and reliability. The tutorial will cover the following topics.
Security for Data in Motion: Inline Memory Encryption & MACsec
This webinar will examine two critical technologies that address these challenges: Inline Memory Encryption (IME) and MACsec (Media Access Control Security).
Protecting the Supply Chain with Secure Provisioning
In this webinar, we’ll dive into secure provisioning and examine how these systems and processes are critical to maintaining the integrity, authenticity, and confidentiality of components and systems as they move from manufacturing to deployment.
Expanding Server Memory Capabilities with MRDIMM Technology
As per socket compute density increases, the amount of directly accessible, low-latency memory bandwidth and capacity to adequately feed data to the multiple cores needs to scale accordingly. Scaling memory bandwidth by increasing raw DRAM component bandwidth or by increasing the number of memory channels has challenges and is reaching limits. JEDEC has unveiled the development of a new DIMM technology called Multiplexed Rank Dual Inline Memory Modules (MRDIMM) to address the bandwidth challenge.
Client DIMM Power Management IC (PMIC5100) Product Brief
Download the product brief to learn how the Rambus PMIC5100 (P1535Gxx) enables client UDIMMs, CUDIMMs, SODIMMs and CSODIMMs. With the Rambus Client Clock Driver and SPD Hub ICs, it comprises a complete memory interface chipset for client DIMMs.
DDR5 MRCD and MDB Product Brief
Download the product brief to learn more about the Rambus DDR5 Multiplexed Registering Clock Driver (MRCD) and Multiplexed Data Buffer (MDB).
