Ensuring reliability in aging chips

This entry was posted on Wednesday, March 28th, 2018.

Ed Sperling of Semiconductor Engineering recently published an article that takes an in-depth look at the concept of ensuring reliability in aging chips.

As Sperling notes, reliability is becoming an increasingly important proof point for new chips as they are introduced to evolving markets such as augmented and virtual reality, automotive, cloud computing and industrial IoT. However, says Sperling, actually proving that a chip will function as expected over time is becoming much more difficult.

“In the past, reliability generally was considered a foundry issue. Chips developed for computers and phones were designed to operate at peak performance for an average of two to four years of normal use,” he explains.

“After that, functionality began to degrade, [with] users upgrading to the next rev of a product, which boasted more features, better performance and longer periods between battery charges. [Today], this is no longer a simple checklist item.”

Use cases, says Sperling, are shifting across the spectrum of electronics.

“This is happening even inside of data centers, which historically have been extremely conservative when it comes to adopting new technologies and methodologies,” he adds.

Indeed, according to Frank Ferro, senior director of product management at Rambus, aging silicon affects various system components, including memory and SerDes PHYs.

“With a PHY, the biggest challenge is ambient temperature. As temperature drives, performance drifts, so you need to do recalibration. [This is why] on the consumer side, there is something called the ‘Christmas Day test,’” he tells Semiconductor Engineering. “In cold weather, you store a Playstation or other electronic device in the garage. Then you turn it on Christmas morning and the circuits need to be able to go from cold to operational instantly. It’s the same for memory systems in a car or a base station [as] aging has an effect on these systems and you have to recalibrate the system to negate those effects.”

As Ferro points out, PHYs undergo the same types of qualifications as digital components, including burn-in and testing for voltage and temperature variation. However, PHYs are designed to change with variations – which are difficult to design into digital circuitry-particularly at advanced nodes, where margining has an impact on power and performance.

Interested in learning more? The full text of “Chip Aging Accelerates” can be read on Semiconductor Engineering here.