The Rambus GDDR6 Memory PHY IP Core
Rambus has officially announced its GDDR6 (Graphics Double Data Rate) Memory PHY IP Core. According to Luc Seraphin, SVP and general manager of the Rambus Memory and Interfaces Division, the PHY is targeted at a number of high-performance applications including cryptocurrency mining, artificial intelligence (AI), ADAS (advanced driver assistance systems) and networking.
“Leveraging almost 30 years of high-speed interface design expertise and using advanced leading-edge FinFET process nodes, the Rambus GDDR6 PHY architecture will provide the industry’s highest speed of up to 16 Gbps, while utilizing established packaging and testing techniques,” he stated.
As Seraphin notes, the high bandwidth delivered by GDDR6 makes it uniquely qualified to perform data-intensive applications such as HPC (high performance computing), AI, autonomous vehicles and high-speed networking.
“We are excited to be the first IP provider to offer a GDDR6 PHY solution with industry-leading performance designed with power efficiency and high-signal margins for these applications,” he added.
Technical Specs and Deliverables:
The JEDEC-compliant Rambus GDDR6 PHY IP Core is optimized for systems that require low-latency and high-bandwidth GDDR6 memory solutions. Available on leading FinFET process nodes, the PHY interface supports two independent channels, with each supporting 16 bits for a total data width of 32 bits. In addition, the PHY supports speeds up to 16Gbps per pin, providing a maximum bandwidth of up to 64GB/s.
Delivered as a fully-characterized hard macro, the Rambus GDDR6 PHY contains all of the necessary components for robust operation, including IO pads, PLL, clock distribution, transmit and receive paths, control logic, power distribution and electrostatic discharge (ESD) protection circuitry.
Additional GDDR6 PHY features include 130um bump pitch; a 13/15-layer metal stack; a DFI-style interface for easy integration with the memory controller; support for Tx de-emphasis and Rx CTLE/DFE for channel optimization; selectable low-power operating states; programmable driver/termination impedance value; built-in test support (ATPG/boundary scans and IO Wrap loopback) and support for 2×16 clamshell mode (DRAM X8 mode enabled).
On the engineering side, the Rambus GDDR6 PHY leverages our system-aware design methodology to facilitate flexible product integration. Specifically, we provide full system signal and power integrity analysis to optimize performance and chip layout. Designed for simplified integration and bring-up, GDDR6 PHY customers receive a hard macro solution, along with a full suite of LabStation™ software that enables quick turn-on, characterization and debug. Moreover, the memory controller or PHY can be set as the ASIC interface master for training and calibrations (PHY independent mode).
Additional deliverables include gate-level and IO models; a Verilog behavior model; layout abstracts (.lef); timing models (.lib); CDL netlists (.cdl); GDSII layout and DRC & LVS reports. The Rambus GDDR6 PHY is also packaged along with full documentation, such as datasheets, package design information, ASIC/DFT manufacturing guidelines, as well as a test and characterization user guide.