Robert H. Dennard co-authored his now-famous paper for the IEEE Journal of Solid State Circuits way back in 1974. Essentially, Dennard and his engineering colleagues observed that as transistors are reduced in size, their power density stays constant. Meaning, power use stays in proportion with area, as both voltage and current scale (downward) with length.
There is a general industry consensus that the laws of Dennard scaling broke down somewhere between 2005-2007. Because threshold and operating voltage cannot be scaled any longer, it isn’t possible to maintain a constant power envelope from generation to generation – while simultaneously achieving the performance gains historically associated with reducing transistor size. Nevertheless, according to Yakun Sophia Shao and David Brooks, the semiconductor industry has already begun to adapt to the loss of Dennard Scaling as the end of Moore’s Law also looms large on the near-term horizon.
“This will likely lead to the additional consolidation in the semiconductor industry and fabrication companies will rely on ‘More-than-Moore’ to prove differentiation,” Shao and Brooks explained in their 2015 book titled Research Infrastructures for Hardware Accelerators. “Without either kind of scaling, there is also a risk of stagnation in the overall computing industry.”
However, Shao and Brooks emphasize that technology disruption often means new opportunities for innovation at the design and architecture level.
“Companies will increasingly differentiate their products based on vertically integrated solutions that leverage new applications mapped to innovative hardware architectures,” they stated. “In this context, application and domain specific hardware accelerators are one of the most promising solutions for improving computing performance and energy efficiency in a future with little benefit from device technology innovation.”
Steven Woo, VP of Systems and Solutions at Rambus, concurs with the assessment offered by Shao and Brooks.
“Although Moore’s Law has facilitated the creation of more transistors per chip for decades, clock speeds are plateauing due to power and thermal limitations. Similarly, improvements in Instructions Per Clock cycle have plateaued as well,” he explained.
“With the traditional paths for improving system performance no longer yielding gains at their historic rates, the industry must focus on rethinking system architectures to drive large improvements in performance and power efficiency.”
Further complicating matters, says Woo, is the fact that traditional performance and power efficiency bottlenecks in systems have shifted over the years due to the evolution of both architecture and applications. Put simply, the relentless progression of Moore’s Law and clock speed scaling prevalent throughout the 1990s and early 2000s so effectively improved computation capabilities that processing bottlenecks have moved to other areas.
“For example, the rise of the Internet of Things (IoT), Big Data analytics, in-memory computing and machine learning has resulted in ever-larger amounts of data being generated and analyzed,” he continued. “In many systems today, so much data is transferred across networks that data movement is itself becoming a critical performance bottleneck. Moreover, the very act of moving data is consuming a significant amount of power, so much so that it’s often more efficient to move the computation to the data instead.”
Consequently, there is an industry-wide effort to re-examine the architecture of conventional computing platforms by reducing and even eliminating certain modern bottlenecks.
“There are a number of recent developments in the industry that address modern HPC and data center bottlenecks such as Near Data Processing. These include the use of various accelerators including GPUs, FPGAs, and specialized processors,” Woo stated. “These industry efforts are focusing on both the hardware and the software infrastructure that ultimately will allow applications to achieve large gains in performance and power efficiency.”
Perhaps most important, says Woo, is to realize that traditional architectures may not be the best choice for certain data intensive workloads because they don’t address key power efficiency and data movement bottlenecks.
“Traditional processors coupled with acceleration hardware such as FPGAs, along with technologies to minimize data movement, offer new approaches to improving performance and power efficiency in modern systems. We believe FPGAs, alongside other acceleration silicon, will continue to play an important role in helping to evolve computing platforms by enabling flexible acceleration and near data processing,” he added.
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