PCIe 4.0 is the next evolution of the ubiquitous and general purpose PCI Express I/O specification. It’s also known as PCIe Gen 4 and it is the fourth generation of Peripheral Component Interconnect Express (PCI express) expansion bus specifications, which are developed, published, and maintained by the PCI Special Interest Group (PCI-SIG).
In this blog, you’ll learn all about PCI express 4 performance vs PCIe 3.0. More specifically:
1. PCIe 4.0 bandwidth
2. Market applications: Who needs PCIe 4.0?
3. PCIe 3.0 vs 4.0: Comparison table
4. Complete PCI express 4 subsystem solutions from Rambus
Read our primer? Jump to: PCI Express 5 vs. 4: What’s New?
PCIe 4.0 bandwidth
The interconnect performance bandwidth is double that of the PCIe 3.0 specification achieving 16GT/s and compatibility with software and mechanical interfaces is preserved. PCIe 4.0 architecture is compatible with prior generations of PCIe technology.
Market applications: Who needs PCIe 4.0?
Big Data needs throughput
According to Gary King, Weatherhead University Professor, “The data flow so fast that the total accumulation of the past two years—a zettabyte—dwarfs the prior record of human civilization”. Internet, ubiquitous smartphone usage and increased marketing accelerated the Big Data revolution and the Internet of Things (IoT) will increase the needs for fast and efficient data management environments. More Throughput and Lower Power are necessary to prevent a bottleneck in the emergence of Big Data.
8-lane and 16-lane PCI Express 3.0 have the bandwidth required to handle a 40Gb Ethernet connection. However, using that many lanes raises cost, packaging, and power issues. A higher speed link requiring fewer lanes would be a much better implementation.
Storage Technologies need more Bandwidth
Data stream provided by PCIe 3.0 (8GT/s) is already sees as a speed limitation for SSD bandwidth. (It can be compared with SAS 12G port that delivers a 12 GT/s data stream). PCIe combined with NVMe will dramatically enhance performance to 16 GT/s per lane.
PCIe 3.0 vs 4.0: Comparison table
There are no encoding changes from 3.0 to 4.0. There were only minor updates in term of protocol. Indeed, evolution to 4.0 is mostly targeted to address the PHY interface. This is expected to be the most challenging issue for designers to solve.
There are also minor changes in terms of link-level management. PCIe 4.0 enables a more robust equalization.
In term of performance, with PCIe 4.0, throughput per lane is 16 GT/s. The link is full duplex, which means the data can be sent and received simultaneously à Total Bandwidth: 32GT/s. No other industry protocol can achieve the bandwidth of the PCIe 4.0 technology (Up to 64 Gbytes/s of total bandwidth for a PCIe 4.0 x16). New emerging interfaces such as: Ethernet 40G/100G, InfiniBand, solid-state drives (SSDs) and flash memory are demanding bigger pipes. These figues make PCIe architecture the only technology solution that achieves this level of performance with minimal new software upgrades.
Complete PCI express 4 subsystem solutions from Rambus
The Rambus PCI Express (PCIe) 4.0 SerDes PHY is designed to maximize interface speed in the difficult system environments found in high-performance computing. It is a low-power, area-optimized, silicon-proven IP designed with a system-oriented approach to maximize flexibility and ease integration for our customers.
In August 2021, Rambus completed the acquisition of PLDA. With this acquisition, Rambus expanded its digital controller offerings with complementary CXL 2.0, PCIe 5.0 and PCIe 6.0 controller and switch IP, and gains critical building blocks for its CXL Memory Interconnect Initiative.
Additionally, with PLDA PCIe 4.0 controller core, we offer a complete PCIe 4.0 SerDes subsystem.
Why choose Rambus’ PCIe 4.0 IP ?
For the reliability:
- Besides our own long-term experience, PLDA’s team has additionally 20+ years of experience in design of IP cores for ASIC with specialization in high-speed interface protocols and technologies,a specific focus on PCIe. More than 5700 customers, with several hundred ASIC tapeouts.
- PCIe 3.0 architecture is already silicon proven in several projects. Proven PCIe 3.0 architecture is preserved to enable easy migration to PCIe 4.0. No interface change is necessary; existing behavior is preserved for seamless integration.
- PLDA’s PCIe 4 Controller IP’s currently uses the PIE-8 specification, enabling easy integration with PCS layers from multiple PHY vendors. PLDA actively participates in PIE-8 2.0 specification update.
For the Flexibility:
Flexibility of the supported PIPE Configurations for PCIe 4.0:
Flexibility of the core configuration to meet spec evolutions
- For the supported features:
Features already proven in 3.0, optimized for the targeted markets of PCIe 4.0
- Endpoint, root port, switch, dual-mode shared silicon
- Virtualization-ready with SRIOV and ATS/ARI (networking, datacenter)
- AER and data integrity mechanism
- Complete power management support: legacy, ASPM L0s/L1, OBFF, L1 PM substate with CLKREQ
- End-end TLP prefixes
- Because it is optimized for PCIe 4.0 challenges
- Re-timer devices are expected to become widespread in PCIe 4.0 motherboards and backlanes.
PLDA IP Core supports Extension Device ECN
Multiple Packets Per Clock Cycle:
PCIe 4.0 is the latest iteration of PCIe to get a commercial release. The two standards are structurally very similar, with the key difference being the higher transfer rate. It offers double the bandwidth than that of its predecessor, PCIe 3.0 and has double the throughput of PCIe 3.0. Rambus provides fully integrated “Controller + PHY” subsystem solutions for PCIe 4.0 to our customers, targeting various foundry/process combinations. If you have design challenges to solve in your current project, we’re more than happy to help. Reach out our Sales specialists.
Keep on reading:
Leave a Reply