SerDes PHYs

As data grows at an accelerating pace, more compute power and bandwidth are required to process this data, driving the need for larger and more complex system on chips (SoCs). This is particularly true at a time when our old friend Moore’s Law has lost a step.

However, as the complexity of SOCs increases, so do the costs to manufacture in leading-edge FinFET geometries. As misery loves company, achieving first-time-right silicon has become more difficult as well. Additionally, there are greater challenges for power scaling and yield. In other words, everything gets harder.

Chip disaggregation, or chiplets, offers an alternative to the traditional monolithic SoC scaling approach. Aggregating multiple chiplets to perform the function of a single monolithic IC de-risks the overall system by reducing complexity and increasing yields.

For applications like artificial intelligence (AI), where there is a “Cambrian explosion” in the number of SoCs and architectural approaches under development, chiplets are an ideal solution. Greater experimentation, and faster time to market are possible when a designer can revise a single chiplet as opposed to having to re-spin an entire SoC.

A key enabling technology required to make chiplet performance on par with that of an SoC is the high-speed interconnects between the chiplets. These must run at extremely high data rates and at very low power.

The Optical Internetworking Forum (OIF) specified the Common Electrical I/O (CEI) 112G XSR (Extra Short Reach) interface to provide the interconnect between chiplets, and between chiplets and optical engines. It is designed for low complexity and very low power while offering extremely high throughput capabilities.

Today, we announced the Rambus 112G XSR SerDes on 7nm FinFET process is now available for licensing. It joins a portfolio of 7nm Rambus PHY solutions including GDDR6, HBM2 and 112G LR (Long Reach) tailored for advanced applications such as AI, advanced driver-assistance systems (ADAS) and hyperscale data centers. With these interface solutions, chip designers can satisfy their need for speed and unleash the power of new compute architectures.

Ken Dyer, Director, Engineering Architecture, is the author of a 112G Long Reach (LR) SerDes PHY article in eeweb.com/EE Times network.

The 112G is coming on to the market to comply with growing demands for greater bandwidth for next generation data centers as well as for advanced applications like artificial intelligence (AI) and machine learning, as well as 5G communications.

Dyer calls Rambus’ 112G LR SerDes PHY “the top contender to boost greater performance with acceptable power and area” for those next generation data center and network systems designs.  His article details the new advanced SerDes PHY. However, he explains to SoC and network system designers that they may want data in different ways.

He said, “They also may opt to have a forward error correction (FEC) on the output of the receiver to improve bit error rate (BER) of the received data.  FEC performs that operation by using redundancy.  It transmits slightly faster than the data required, hence extra information is transmitted.  By reviewing the extra information in the received signal, FEC determines if mistakes have occurred or not.”

Dyer calls special attention to today’s higher serial data rates and added that four-level pulse amplitude modulation or PAM-4 has made its entrance and explained how it plays into the 112Gbps SerDes PHY.

He said that “We first need to look at Nyquist loss for NRZ data for a generic legacy channel and for 112Gbps data transmission. Nyquist loss is the insertion loss of the input signal at half the symbol rate.  For NRZ at 112Gbps, its nominally 56GHz. NRZ is two-level data and it’s at a relatively low 70 decibels (dB) at 56 Gigahertz (GHz).

“In short, crosstalk has more power than the signal, hence signal-to-noise ratio (SNR) is negative.  This means error-free communication or signal recovery is not possible.  In this case, if a transmitter is operated at 56Gpbs, data would not be received at all. Therefore, PAM-4 becomes a more viable solution than the traditional NRZ (non-return-to-zero).”

Be looking for sequels to this first 112G LR article in eeweb.com/EE Times network.  Articles, like this one, are designed to help SoC and data center system designers to prepare their next generation designs.

Rambus has officially announced the 112G Long Reach (LR) SerDes PHY. Hemant Dhulla, VP and GM of IP Cores, said, “By leveraging leading 7nm process technology, Rambus is enabling the next generation of communications and data center applications.”

He further stated, “We’re excited to continue to expand our IP portfolio and deliver our customers top-of-the-line performance and flexibility for today’s most challenging systems, including solutions like our 112G LR SerDes PHY.”

As the industry rapidly transitions to 400GB and 800GB wired communication applications, 112G is a key building block necessary to support the ever-growing demand for more bandwidth in data center and network applications, doubling the data rate of 56G SerDes.

Rambus is at the forefront of implementing 112G design to address the long-reach backplane requirements for next-generation data-intensive applications. Those applications include generation terabit switches, routers, optical transport networks (OTNs), and high-performance networking equipment.

The new Rambus 112G LR SerDes PHY provides the optimal combination of power efficiency, performance and area, adding to Rambus’ leading-edge large portfolio of silicon-proven intellectual property (IP), design tools and reference flows. With the introduction of 112G, this technology achieves higher performance to rapidly enable industry infrastructure for the 400GB and 800GB applications.

The 112G LR SerDes PHY uses both PAM4 and NRZ (PAM2) signaling to provide reliable operation across a broad range of data rates. As such, they support legacy protocols, and provide the scalability to achieve the highest levels of performance.

They are built on a configurable architecture, enabling power to be matched to the channel loss. An embedded micro-processor enables firmware-controlled PMA configuration, initialization and adaption for maximum flexibility with minimum SoC integration effort.

The 112G LR SerDes PHY also provides SoC and system designers two other key features.  Its DSP-based architecture hands them improved signal to noise (SNR) and extended reach.  Plus, the 112G is configurable to provide power, performance, and area (PPA) optimization for medium reach (MR) and long reach (LR) applications.

This latest portfolio addition highlights Rambus leadership in high-speed SerDes PHY IP, leveraging the company’s long tradition of signal and power integrity expertise — remaining at the forefront of innovation in interface technology.

For more on the Rambus 112G LR SerDes PHY, check out our eBook.

In 2005, Samsung launched its Foundry business to provide leading-edge technology to the broader market. Based on accumulated technology leadership, Samsung successfully developed the foundry industry’s first 32nm High-k Metal Gate (HKMG) process in 2010, and started the first 14nm Fin Field Effect Transistor (FinFET) product’s mass production

The third annual Samsung Foundry Forum (SFF) in the United States is set to take place on May 22^nd, 2018 at the Santa Clara Marriott, where industry leaders will share their latest innovations in process technology, IP, design tools, design services, and packing for established and emerging applications.

Rambus is participating in SFF as a Samsung Advanced Foundry Ecosystem (SAFE™) partner. “Samsung Foundry is our strategic partner on an IP development front, specifically for High-Speed SerDes in 14nm and 10 nm.” says Mohit Gupta, Senior Director of Product Marketing at Rambus’ Memory and Interfaces Division. “We play an important role as part of their IP ecosystem and at SFF this year, we are focused on our 28G and 56G SerDes IP offerings.”

A worldwide event, SFF is revamping its efforts in hopes of being a credible pure play Foundry. With other SFFs happening in Santa Clara, Seoul, and Shanghai, Rambus hopes to participate in North America, South Korea, China, and possibly EMEA. “Samsung is doing worldwide foundry forums to promote Samsung Foundry and its partners. Participating here gives us broader visibility with our target customer base for our Samsung Foundry IP,” says Hemant Dhulla, Rambus’ Vice President of Product Marketing.

Rambus’ 28G and 56G SerDes

Rambus will be discussing 28G and 56G SerDes offerings for 14nm and 10nm. Also, our 56G solution uses an Analog to Digital Converter (ADC) based long-reach (LR) design for backplane applications. Rambus can also offer a power optimized version for medium and short reach application if there is customer interest. Rambus is also the exclusive supplier for 56G on SS10.

The Samsung-Rambus Partnership

Rambus’ partnership with Samsung has produced other great products like the SS14 28G SerDes, which is deployed on multiple ASICs in the wireless and wired communication space. Gupta says that Rambus will “continue to support Samsung Foundry based on customer requests and demand to address the needs on high speed interfaces.” Moreover, Dhulla says that showcasing Rambus’ IP demonstrates solid partnership with Samsung Foundry, which will create pull from the target customer base.

The Bottom Line

As an effort to provide cutting-edge semiconductor technology to the broader market, Samsung Foundry was established, with SFF showcasing innovational products worldwide. As a SAFE™ ecosystem partner, Rambus is helping to achieve that vision through its partnership with Samsung.

HBM2 @ 256GB/s

As Semiconductor Engineering’s Ann Steffora Mutschler observes, high-bandwidth memory (HBM) enables lower power consumption per I/O, as well as higher bandwidth memory access with a more condensed form factor. This is accomplished by stacking memory dies directly on top of each other – and sharing the same package as an SoC or GPU core using a silicon interposer. Each pin drives a much shorter trace and runs at a lower frequency – resulting in significantly lower switching power.

“High-bandwidth performance gains are achieved by a very wide I/O parallel interface,” Mutschler explains.

“HBM1 can deliver 128GB/s, while HBM2 offers 256GB/s maximum bandwidth. Memory capacity is easily scaled by adding more dies to the stack – or adding more stacks to the system-in-package.”

As Frank Ferro, a senior director of product management at Rambus notes, HBM takes existing DRAM with 2.5D technology and moves it closer to the processor using a fatter data pipe. This paradigm accelerates data throughput – effectively reducing the amount of power required to drive a signal and cutting RC delay.

“Originally, high-bandwidth memory was seen by the graphics companies as a clear step in the evolutionary direction,” Ferro tells Semiconductor Engineering. “But then the networking and data center community realized HBM could add a new tier of memory in their memory hierarchy for more bandwidth and all the things that are driving the datacenter: lower latency access, faster access, less delay and lower power. As a result, HBM design activities have picked up pace in these market segments.”

HBM design challenges

Perhaps not surprisingly, there are a number of HBM design factors that must be taken into consideration. For example, the challenge from a system design perspective often revolves around fitting more bandwidth in a reasonable area on the chip – and within a reasonable power profile. In general, HBM is considered quite efficient from a power and area perspective because it exploits 3D stacking technology.

“[However], the tradeoff here is cost, as HBM 2 is more expensive. So far, the primary applications of this technology are tied to some form of advanced packaging—2.5D or high-end fan-outs—which have been developed with high-performance in mind rather than cost,” Mutschler elaborates. “The alternative is some combination of DDRs and/or GDDRs, which can be combined to achieve more performance than a traditional DRAM solution. [However, this configuration would] require a larger area and more chips.”

Indeed, says Ferro, companies have to decide if they want to use 5 or 10 DDRs, multiple GDDRs or a single HBM stack.

“What are the system tradeoffs, power tradeoffs and performance tradeoffs? [These are important questions to consider], because SerDes has been driving up to 56 or 112 GB,” he tells the publication. “So, there are all of these very high-speed links in the system and now you’re moving data very rapidly, but now you have to start to store it and process it very rapidly, too. As a result, we continue to see in the networking market and in the enterprise market [engineering teams asking] how to get more memory bandwidth to go with all this moving of data around.”

HBM, GDDR6 and automotive memory

Ferro also notes that while power is always an important consideration, there is more of an emphasis on cost versus bandwidth in the automotive sector. Put simply, performance and price are neck and neck, with power coming in at third place.

“Chipmakers are looking at memory systems that can handle bandwidth greater than 100 Gbps and higher as you get into different levels of driver assisted cars – and ultimately self-driving cars,” Ferro tells Semiconductor Engineering. “In order to do that, the number of memory choices starts to narrow down quite a bit in terms of what can provide you with the necessary bandwidth to process all that data that is coming in.”

As Ferro points out, some of the early advanced driver-assistance systems (ADAS) system designs included both DDR4 and LPDDR4 because that was what was available at the time, although have their advantages and disadvantages.

“DDR4 is obviously the cheapest option available and those are in the highest-volume productions,” he adds. “They are certainly very cost-effective and very well understood. Doing error correction on DDR4 is simpler and well understood. LPDDR4 was also an option that was used, as well.”

Moving forward, says Ferro, the automotive industry can expect a range of memory types to coexist in different systems.

“If [systems] are heavily cost-driven, then they are going to be looking at something like DDR or maybe even LPDDR4,” he states. “But if they are heavily bandwidth-driven, [system designers] will be looking at something like HBM or GDDR. It’s really a function of where you are in your architecture stage.”

In addition, says Ferro, there are also various levels of ADAS capabilities to consider, as well as what’s required for the system and shipping timeframe.

“If you are getting a system shipping this year, it would have a different solution than systems being developed for next year or the year after that,” he continues. “Those are all the things that we are seeing on the continuum of time-to-market versus cost.”

On the high-performance side, says Ferro, the bandwidth-power tradeoff is the key challenge from a system-design standpoint. For example, how does an engineer get more bandwidth to fit in a reasonable area on a chip with reasonable power consumption?

“If you have an HBM [design], it is very efficient from a power and area standpoint because it uses 3D stacking technology, so from a power efficiency point of view, HBM is fantastic,” he concludes. “And from an area standpoint, one HBM stack takes up a relatively small amount of space, so that’s a really nice-looking solution from a power-performance perspective. You get great density, you get great power, low power, within a small area.”