CXL
CXL™ 3.0 Turns Up Scalability to 11
The CXL™ Consortium (of which Rambus is a member) has now released the 3.0 specification of the Compute Express Link™ (CXL) standard. CXL 3.0 introduces
August 2, 2022
Primers
PCIE 6.0 – All you need to know about PCI Express Gen6
While the PCI-SIG has announced that the release of the PCI Express® 6.0 (PCIe 6.0) specification should arrive in 2022, Rambus is already addressing the needs of early adopters looking for the most advanced PCIe 6.0
September 22, 2022
SerDes PHYs
What is PCIe 4.0? PCI Express 4 explained
PCIe 4.0 is the next evolution of the ubiquitous and general purpose PCI Express I/O specification. It’s also known as PCIe Gen 4 and it
November 2, 2021
SerDes PHYs
New interface architectures enable data scaling
Suresh Andani, senior director of product marketing at Rambus, has written an article for Semiconductor Engineering that takes a closer look at why data center
April 8, 2022
SerDes PHYs
Designing chiplet and co-packaged optics architectures with 112G XSR SerDes
Suresh Andani, senior director of product marketing at Rambus, has written an article for Semiconductor Engineering that takes an in-depth look at how 112G XSR
May 18, 2021
SerDes PHYs
Overcoming high-speed SerDes IP integration challenges: Part 2
In this two-part blog series based on a recent Semiconductor Engineering article, Rambus engineers Niall Sorensen and Malini Narayana Moorthi take an in-depth look at
April 25, 2021