SerDes PHYs
New interface architectures enable data scaling
Suresh Andani, senior director of product marketing at Rambus, has written an article for Semiconductor Engineering that takes a closer look at why data center
June 3, 2021
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SerDes PHYs
Designing chiplet and co-packaged optics architectures with 112G XSR SerDes
Suresh Andani, senior director of product marketing at Rambus, has written an article for Semiconductor Engineering that takes an in-depth look at how 112G XSR
May 18, 2021
SerDes PHYs
Overcoming high-speed SerDes IP integration challenges: Part 2
In this two-part blog series based on a recent Semiconductor Engineering article, Rambus engineers Niall Sorensen and Malini Narayana Moorthi take an in-depth look at
April 25, 2021
SerDes PHYs
Overcoming high-speed SerDes IP integration challenges: Part 1
Rambus engineers Niall Sorensen and Malini Narayana Moorthi recently wrote an article for Semiconductor Engineering that takes an in-depth look at how to overcome high-speed
April 12, 2021
Memory PHYs
HiPEAC Tech Transfer Award Highlights DRAMSys4.0 Collaboration
HiPEAC, a European network of almost 2,000 world-class computing systems researchers, named Matthias Jung (Fraunhofer IESE), Lukas Steiner, and Norbert Wehn (TUK) as winners of
January 13, 2021
HBM and GDDR6
The Ultimate Guide to HBM2E Implementation & Selection
This is the most comprehensive guide to selecting and implementing a HBM2E memory IP interface solution. Recently, Frank Ferro and Joseph Rodriguez, Senior Directors Product
December 16, 2020