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SerDes PHYs

Google wants 5 petabit switching

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The Platform’s Timothy Prickett Morgan reports that Google is eyeing networking throughput capabilities of 5 petabits per second. However, as Google Fellow Amin Vahdat recently pointed out, the industry currently “underprovisions” networks because it doesn’t (yet) know how to build big networks capable of delivering “lots” of bandwidth.

According to Vahdat, the ideal network should have 1 Mbit/sec of I/O for every 1 MHz of computation to maintain a balanced system in a parallel computing environment.

“[He] pointed out that with the adoption of flash today and other non-volatile memories in the future, which have very high bandwidth and very low latency requirements, keeping the network in balance with compute and storage is going to be a big challenge,” writes Morgan.

Image Credit: The Platform (via Google)

To illustrate his point, Vahdat discussed a hypothetical data center (see image above) populated by 32-core processor servers running at 2.5 GHz. The servers are equipped with 100 Gb/sec ports that reach out into the datacenter network.

Commenting on the above report, Mohit Gupta, a director of product marketing at Rambus, says there is a definite need to move from a 10Gbps serial link data rate to 25Gbps or 50Gbps and perhaps even higher as bandwidth and capacity requirements continue to increase.

“Moving to higher data rate links in data centers and servers improves overall efficiency. For example, a 100GbE implemented in 10x10Gbps configuration significantly bolsters overhead, especially in comparison to 4x25Gbps systems,” he explained. “Of course, higher data rate serial links are more complex and challenging to design. Remember, systems needs to run higher speeds (2.5x) for the same cables, traces and backplanes – all while supporting backwards compatibility for legacy standards running at 1.25Gbps.”

Gupta also noted that the power-performance ratio is another important variable to keep in mind when it comes to increasing data rates.

“Perhaps the biggest cost involved in running a data center is electricity consumption,” he added. “As such, there is a considerable amount of emphasis on keeping the power low for such links – even though they are targeted for higher speeds. This poses additional challenges for both system and serial link designers.”

Shrinking nanometers with Rambus and Globalfoundries

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Globalfoundries – which operates a total of 8 semiconductor fabrication facilities across the globe – has a long history of collaborating with Rambus on a wide variety of projects.

In 2011, the two industry heavyweights began working closely together on the foundry’s 28-nanometer super low power (28nm-SLP) process, with Globalfoundries’ assembly support team also providing wirebond and flipchip packaging options on high-speed PHY designs.

Two separate memory architecture-based 28nm silicon test chips were subsequently announced in July 2012. The first piece of silicon targeted smartphones and tablets, while the latter was designated for servers, or compute main memory applications.

As Sunil Bhardwaj, a director of strategic partnerships at Rambus points out, new chip starts and IP enablement are becoming infinitely more complex.

“The cost of productizing process technology, new chip implementation, advanced EDA tools and a comprehensive IP portfolio is now a prohibitively expensive endeavor,” Bhardwaj told Rambus Press.

“In addition, demand for faster time to market, lower cost, and reduced power consumption, has increased concurrently. This is why it is critical for ecosystem companies to collaborate on reducing overhead, as well as to continuously scale and demonstrate technology to ensure a low-risk, rapid industry adoption.”

As we noted previously, Rambus and Globalfoundries have worked together in such a manner by demonstrating the capabilities of 28nm, advanced foundry processes and Rambus R+ design innovations.

“We complement each other’s offerings, all while highlighting the production readiness of the design enablement ecosystem of both Globalfoundries’ foundry and Rambus IP customers,” Bhardwaj explained.

“For example, R+ IP products benefit from Globalfoundries’ design enablement support and expertise, including process design kits (PDKs), DFM kits, analog mixed signal reference flow, extensive implementation services and silicon proven logic libraries.”

Most recently, says Rambus exec Joe Gullo, the two companies have collaborated on both low-power and high performance designs, with silicon demos (in progress) of low-power memory PHYs targeting industry standard, as well as beyond data-rates and multi-protocol high speed serial links.

“The divergent power performance requirements from these separate IP product families highlight the comprehensiveness of the 28nm foundry platform,” he added.

“We look forward to collaborating with the industry and Globalfoundries to scale and productize these IP platforms to 14nm and beyond.”