
Understanding HBM design challenges
HBM2 @ 256GB/s As Semiconductor Engineering’s Ann Steffora Mutschler observes, high-bandwidth memory (HBM) enables lower power consumption per I/O, as well as higher bandwidth memory
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HBM2 @ 256GB/s As Semiconductor Engineering’s Ann Steffora Mutschler observes, high-bandwidth memory (HBM) enables lower power consumption per I/O, as well as higher bandwidth memory
From 400 Gbps to 800 Gbps A recently published report by the Dell’Oro Group states that 400 Gbps is expected to comprise 20 percent of
EDN’s Martin Rowe wrote an article that explores various industry viewpoints – shared at a DesignCon 2018 panel – about the future of NRZ vs PAM4
Niraj Mathur, VP of high speed interface products at Rambus, recently penned an article for Semiconductor Engineering that explores the importance of PCI Express 4.0 in
Rambus’ silicon-proven, high-speed SerDes solutions Rambus is now offering a suite of silicon-proven, high-speed SerDes solutions developed for the GLOBALFOUNDRIES high-performance FX-14™ ASIC platform. The
Semiconductor Engineering’s Anna Steffora Mutschler has written an article about how peak power poses a serious design challenge for chips, electronic systems and data centers.