
Complete Interface Solution for PCIe 5.0 Launched
Rambus has announced a comprehensive interface solution for PCI Express 5 (PCIe 5.0) consisting of a new PCIe 5.0 PHY and a co-verified Northwest Logic
Home > SerDes PHYs > Page 3
Rambus has announced a comprehensive interface solution for PCI Express 5 (PCIe 5.0) consisting of a new PCIe 5.0 PHY and a co-verified Northwest Logic
As data grows at an accelerating pace, more compute power and bandwidth are required to process this data, driving the need for larger and more
Ken Dyer, Director, Engineering Architecture, is the author of a 112G Long Reach (LR) SerDes PHY article in eeweb.com/EE Times network. The 112G is coming
Rambus has officially announced the 112G Long Reach (LR) SerDes PHY. Hemant Dhulla, VP and GM of IP Cores, said, “By leveraging leading 7nm process technology,
Hemant Dhulla, vice president and general manager of IP Cores at Rambus says that the newly announced 28G and 32G SerDes from Rambus “will be
In 2005, Samsung launched its Foundry business to provide leading-edge technology to the broader market. Based on accumulated technology leadership, Samsung successfully developed the foundry