Mohit Gupta, a senior director of product marketing for Rambus’ Memory and Interfaces Division, has penned an article for Semiconductor Engineering about the growing industry interest in SoC/ASIC disaggregation.
As Gupta notes, petabytes of data are continuously generated by a wide range of devices, systems and IoT endpoints such as vehicles, wearables, smartphones and even appliances. The resulting digital tsunami has prompted industry heavyweights like Google, Microsoft, Facebook and Amazon to consider implementing and innovating new architectures in the data center to remove bottlenecks.
“After years of steady SoC/ASIC aggregation, a disaggregated approach is now seriously being considered in the form of SerDes chiplets and specialized low-power, application-specific die-to-die interfaces,” he explained. “The concept of SoC/ASIC disaggregation is certainly timely, as demands for higher bandwidth within a similar power envelope will only increase.”
According to Gupta, designing silicon on more advanced process nodes is clearly one option, although the costs at 7nm and beyond are quite high. Moreover, developing mixed-signal silicon on consecutive nodes is both challenging and expensive. To further complicate matters, SoC designs are fast approaching the outer limits of both yield capabilities and reticle size architecture.
“However, die-to-die interfaces can more easily accommodate multiple applications across memory, logic and analog technology,” he stated. “In addition, die-to-die interfaces do not require a matching line/baud rate and number of lanes. Moreover, forwarded clock architecture provides a low power solution, while FEC may or may not be required depending upon latency requirements.”
A number of companies, says Gupta, are already actively pursuing SoC/ASIC aggregation for switches and other systems. Similarly, the industry is developing ASICs with die-to-die interfaces on leading FinFET nodes, while at least one next-generation server chip is being designed with disaggregated IOs on a separate die.
“Understanding the advantages of SoC/ASIC disaggregation can help the semiconductor industry evolve on both a micro (silicon) and macro level (data center). With SoC designs fast approaching the outer limits of both yield capabilities and reticle size architecture, the concept of disaggregation has never been timelier,” he concluded.