
PCIe 5 Drill-Down with Rambus’ Suresh Andani: Part 2
In part one of this three-part series, Semiconductor Engineering Editor in Chief Ed Sperling and Suresh Andani, Senior Director, Product Marketing and Business Development at
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In part one of this three-part series, Semiconductor Engineering Editor in Chief Ed Sperling and Suresh Andani, Senior Director, Product Marketing and Business Development at

Semiconductor Engineering Editor in Chief Ed Sperling recently sat down with Suresh Andani, Senior Director, Product Marketing and Business Development at Rambus, to discuss the

Rambus has announced a comprehensive interface solution for PCI Express 5 (PCIe 5.0) consisting of a new PCIe 5.0 PHY and a co-verified Northwest Logic

As data grows at an accelerating pace, more compute power and bandwidth are required to process this data, driving the need for larger and more

Ken Dyer, Director, Engineering Architecture, is the author of a 112G Long Reach (LR) SerDes PHY article in eeweb.com/EE Times network. The 112G is coming

Rambus has officially announced the 112G Long Reach (LR) SerDes PHY. Hemant Dhulla, VP and GM of IP Cores, said, “By leveraging leading 7nm process technology,
