In part one of this three-part series, Semiconductor Engineering Editor in Chief Ed Sperling and Suresh Andani, Senior Director, Product Marketing and Business Development at
Semiconductor Engineering Editor in Chief Ed Sperling recently sat down with Suresh Andani, Senior Director, Product Marketing and Business Development at Rambus, to discuss the
Introduction What’s new about PCI Express 5 (PCIe 5)? The latest PCI Express standard, PCIe 5, represents a doubling of speed over the PCIe 4.0
Rambus has announced a comprehensive interface solution for PCI Express 5 (PCIe 5.0) consisting of a new PCIe 5.0 PHY and a co-verified Northwest Logic
As data grows at an accelerating pace, more compute power and bandwidth are required to process this data, driving the need for larger and more
Ken Dyer, Director, Engineering Architecture, is the author of a 112G Long Reach (LR) SerDes PHY article in eeweb.com/EE Times network. The 112G is coming
