SerDes PHYs

Mohit Gupta, a senior director of product marketing for Rambus’ Memory and Interfaces Division, has penned an article for Semiconductor Engineering about the growing industry interest in SoC/ASIC disaggregation.

As Gupta notes, petabytes of data are continuously generated by a wide range of devices, systems and IoT endpoints such as vehicles, wearables, smartphones and even appliances. The resulting digital tsunami has prompted industry heavyweights like Google, Microsoft, Facebook and Amazon to consider implementing and innovating new architectures in the data center to remove bottlenecks.

“After years of steady SoC/ASIC aggregation, a disaggregated approach is now seriously being considered in the form of SerDes chiplets and specialized low-power, application-specific die-to-die interfaces,” he explained. “The concept of SoC/ASIC disaggregation is certainly timely, as demands for higher bandwidth within a similar power envelope will only increase.”

According to Gupta, designing silicon on more advanced process nodes is clearly one option, although the costs at 7nm and beyond are quite high. Moreover, developing mixed-signal silicon on consecutive nodes is both challenging and expensive. To further complicate matters, SoC designs are fast approaching the outer limits of both yield capabilities and reticle size architecture.

“However, die-to-die interfaces can more easily accommodate multiple applications across memory, logic and analog technology,” he stated. “In addition, die-to-die interfaces do not require a matching line/baud rate and number of lanes. Moreover, forwarded clock architecture provides a low power solution, while FEC may or may not be required depending upon latency requirements.”

A number of companies, says Gupta, are already actively pursuing SoC/ASIC aggregation for switches and other systems. Similarly, the industry is developing ASICs with die-to-die interfaces on leading FinFET nodes, while at least one next-generation server chip is being designed with disaggregated IOs on a separate die.

“Understanding the advantages of SoC/ASIC disaggregation can help the semiconductor industry evolve on both a micro (silicon) and macro level (data center). With SoC designs fast approaching the outer limits of both yield capabilities and reticle size architecture, the concept of disaggregation has never been timelier,” he concluded.

Rambus is attending the Samsung Foundry Forum at the Santa Clara Marriott on May 24^th. The company will be showcasing its 56G SerDes PHY, which is being developed on Samsung’s 10nm LPP (Low-Power Plus) process technology.

As we’ve previously discussed on Rambus Press, our 56G SerDes PHY supports PAM-4 and NRZ signaling and data rates from 9.95Gbps to 58Gbps across copper and backplane channels with more than 35dB insertion loss. At the heart of the SerDes architecture is an ADC (analog to digital converter) operating at 28 GS/s that allows for adjustable power consumption and improved performance while providing low BER (Bit Error Rate) for enterprise class reliability.

Key product highlights include an analog Rx CTLE with combined 12 dB of peaking gain, digital Tx/Rx FFE and DFE, support for Ethernet auto negotiation and multiple lane configurations to facilitate flexible ASIC floorplan integration. The 56G MPS also offers BIST with PRBS generators and checkers, extensive debug capabilities and interfaces using an internal microprocessor, as well as LabStation™ software and scripts for enhanced bring-up and validation.

Additional features include support for up to 8 duplex Lanes and data rates in the range of 9.95 Gbps – 58 Gbps, RX front end with on-chip capacitors to support both AC-coupled and DC-coupled channels, configurable architecture that enables power saving models for low and medium loss channels, as well as a flexible ASIC interface for sharing impedance codes amongst multiple PMAs and reducing the number of external reference resistors for on-chip impedance calibration.

The 56G MPS also offers programmable TX/RX equalizers, a centralized LC-PLL that supports a wide range of reference clock frequencies and lane operating frequencies, differential reference clock inputs that are selectively sourced from dedicated pins or internal ASIC interface pins, direct register control for all PMA functions, as well as a flexible layout to support placement along all edges in an ASIC.

Interested in learning more about our 56 Gbps multi-protocol SerDes PHY? You can check out our product page here and download our product brief here.

Mohit Gupta, senior director of product marketing for Rambus’ Memory and Interfaces Division, recently penned an article for Semiconductor Engineering that explores the connection between SerDes and terabit Ethernet.

According to Gupta, 400 Gigabit Ethernet (400GbE) and 200 Gigabit Ethernet (200GbE) are currently slated for official release by the IEEE P802.3cd Task Force in December 2017.

“Although there is not yet an official IEEE roadmap detailing what lies beyond 400GbE, doubling to 800GbE will likely become a reality when single-lane 112Gbps links hits the market,” he explained. “This technology will allow for larger lane bundles, providing 1 TbE or 1.6 TbE link with 10 or 16 lanes, respectively.”

As Gupta notes, Amazon, Facebook and Google are moving to 100GbE connections in 2017 and are expected to begin purchasing 400GbE systems by 2019.

“It is therefore important for the current generation of 56Gbps SerDes PHYs to meet the long-reach backplane requirements for the industry transition to 400GbE Ethernet applications,” he stated. “This allows the SerDes PHY to scale to speeds as fast as 112Gbps, which are required in the networking and enterprise segments, such as enterprise server racks that are moving from 100GbE to 400GbE and beyond.”

Ethernet is clearly moving faster than ever, due to the rise of Big Data, the Internet of Things (IoT) and other trends that place increasingly high demands on communication channels. In fact, there is already a forum for 112Gbps SerDes which will be critical in driving the 800GbE standard forward. Supporting faster Ethernet speeds, says Gupta, presents a distinct set of challenges for SerDes designers. In addition to maintaining signal integrity, engineers must contend with a stringent set of design requirements, such as architecting next-generation silicon within the same power envelope – without the support of Dennard Scaling.

“Although lower process nodes facilitated by Moore’s Law are obviously beneficial, there are numerous design tradeoffs, specifically around area and power, that should be carefully considered,” he continued. “To be sure, one of the biggest costs involved in running a data center is electricity consumption, so there has always been a significant emphasis on keeping the power low for such links – even though they are targeted for higher speeds.”

According to Gupta, the ideal paradigm for a high-speed, next-generation SerDes that supports Terabit Ethernet is one that maximizes performance with the lowest power draw and smallest area. However, a more realistic scenario would see compromises on performance, power and area, with trade-offs based on specific product requirements.

For example, he says, engineers may want to consider designing a lower reach SerDes that is cheaper on power/area and uses additional components on board such as re-timers to stay within the same budget. In addition, the channel can be made smooth enough to take off some SerDes equalization to maximize power and area efficiency. Moreover, extra PLL/VCO’s can be eliminated, while the merits and extent of backwards compatibility should be assessed.

“Ethernet speeds are fast approaching 800GbE and beyond. Since SerDes PHYs will be playing an important part in the development of terabit Ethernet, system architects should carefully consider the pros and cons of design tradeoffs around area and power. Deciding on a specific set of tradeoffs for high-speed serial links may very well be one of the most stressful parts of the entire design process, although it is critical for maximizing operational efficiency at 400 GbE and beyond,” he concluded.

Rambus is currently collaborating with PLDA and Avery Design Systems Inc. to offer a comprehensive, silicon-proven PCI Express (PCIe) 4.0 solution, with backward compatibility to PCIe 3.0 and 2.0. According to Bill Fuller, a senior director of field application engineering at Rambus, the new PCIe sub-system includes the Rambus SerDes PHY, the PLDA PCIe controller and Avery Design’s verification IP. The solution is pre-verified and validated for simple integration into application-specific integrated circuits (ASICs).

“Our collaboration with PLDA and Avery Design offers customers a complete, pre-verified PCIe sub-system, with silicon-proven SerDes and a PCIe controller,” said Fuller. “Our line-up of SerDes PHYs is optimized for power and efficiency, delivering maximum performance and flexibility for today’s most challenging systems for a variety of applications including networking, data center and high-performance computing.”

As Fuller notes, the Rambus PCIe 4.0 PHY IP, which seamlessly connects to PIPE 4.2-compliant third-party controllers, is a low-power, area-optimized and silicon-proven IP designed with a system-oriented approach to facilitate easy integration and maximize flexibility. The PHY IP consists of a hard Physical Media Attachment (PMA) designed with a minimal set of broadside control and status pins, as well as a soft-configurable Physical Coding Sublayer (PCS), to support a wide range of applications. These include storage and memory connectivity, hybrid storage systems, server connectivity, as well as ASIC, FPGA and GPU interfacing.

“The PHYs have a minimal set of broadside control and are configurable in x2, x4 and x8 lane configurations. This gives the PHYs improved flexibility and support for a wide range of applications. The PCIe 4.0 PHYs are also rigorously tested through third party compliance testing and internal interoperability system testing,” Fuller explained. “Moreover,

to improve system margin and performance, our solution features transmit and receive equalization and full equalization adaptation. This ensures that data is recovered even in the presence of channel and system interference.”

Additional features include:

• Automatic calibration of key circuits to maximize performance and yields
• In-situ real-time monitoring and receive data eye schmo
• Flexible ASIC clocking
• Tight skew control of 2UI between lanes of the PMA
• 3-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
• Deterministic latency within +-1UI variation for Tx lane
• Continuous time linear equalizer (CTLE) with programmable settings providing up to 12dB gain peaking at Nyqvist frequencies
• 6-tap Rx DFE (decision feedback equalizer)
• Second-order CDR meeting SSC and RX sinusoidal jitter requirements
• Expandable register interface enabling communication with multiple PMAs and PCS-BIST soft macros
• Built-in Self Test (BIST) with ATPG and AC/DC Boundary scan support
• Built-in PRBS pattern generation and checking for standalone loopback testing
• Operation across a wide temperature range (-40 C to +125 )
• Support for bifurcation and quadfurcation modes
• Includes ESD structures
• SRIS support

Rambus’ PCIe 4 SerDes PHYs are available on TSMC, Global Foundry and Samsung process nodes. For additional information, please visit our PCIe 4 SerDes PHY product page on Rambus.com here.

Rambus has confirmed that its recently launched 56G SerDes PHY will be developed on Samsung’s 10nm LPP (Low-Power Plus) process technology.

According to Luc Seraphin, senior vice president and general manager of the Rambus Memory and Interfaces Division, the 56G SerDes PHY delivers enterprise-class performance across the challenging signaling environments typical of high-speed communication systems and provides PAM-4 and NRZ signaling with a scalable ADC-based (analog-to-digital converter) architecture.

The new, flexible architecture addresses the long-reach backplane requirements for the industry transition to 400 GB Ethernet applications.

“There is a demand for increased bandwidth and higher performance systems with the rise of data across enterprise applications,” Seraphin explained. “Our partnership with Samsung enables us to bring more solutions quickly to market that address the process, power and performance challenges of today’s complex data centers. We are pleased Samsung has selected to work with us, following our successful partnership of the 28G SerDes PHY on their 14nm LPP process technology.”

Ryan Lee, vice president of the Foundry Marketing Team at Samsung Electronics, expressed similar sentiments.

“Network application is one of our key segments of focus and the composition of our 10LPP network solution and the Rambus 56G solution will be the most competitive choice for high-performance and low-power consumption,” said Lee. “Rambus has been a long-term strategic partner with Samsung for high-speed SerDes IP and this 56G SerDes collaboration will pave the way for the explosive data processing requirements to come.”

With a scalable ADC-based (analog-to-digital converter) architecture, the Rambus 56G SerDes FinFET PHY provides both PAM-4 and NRZ signaling, offering a flexible solution that addresses the needs of long-reach backplane requirements as the industry transitions from 100Gb to 400Gb Ethernet applications.

According to Bill Fuller, senior director of field application engineering at Rambus, the 56 Gbps Multi-Protocol SerDes (MPS) PHY is a PAM-4 and NRZ compliant IP solutions that offers reliable performance across challenging long-reach data center environments.

“The 56G MPS supports PAM-4 and NRZ signaling and data rates from 9.95Gbps to 58Gbps across copper and backplane channels with more than 35dB insertion loss,” he explained. “At the heart of the SerDes architecture is an ADC (analog to digital converter) operating at 28 GS/s that allows for adjustable power consumption and improved performance while providing low BER (Bit Error Rate) for enterprise class reliability.”

As Fuller notes, the 56G MPS is designed with a system-oriented approach that takes the interface, interconnect and channel into account when optimizing performance and features to maximize flexibility in today’s most challenging system environments and applications.

“This makes the PHYs ideal for many long-reach, copper and backplane enterprise environments,” he stated.

Key product highlights include an analog Rx CTLE with combined 12 dB of peaking gain, digital Tx/Rx FFE and DFE, support for Ethernet auto negotiation and multiple lane configurations to facilitate flexible ASIC floorplan integration. The 56G MPS also offers BIST with PRBS generators and checkers, extensive debug capabilities and interfaces using an internal microprocessor, as well as LabStation™ software and scripts for enhanced bring-up and validation.

Additional features include support for up to 8 duplex Lanes and data rates in the range of 9.95 Gbps – 58 Gbps, RX front end with on-chip capacitors to support both AC-coupled and DC-coupled channels, configurable architecture that enables power saving models for low and medium loss channels, as well as a flexible ASIC interface for sharing impedance codes amongst multiple PMAs and reducing the number of external reference resistors for on-chip impedance calibration.

The 56G MPS also offers programmable TX/RX equalizers, a centralized LC-PLL that supports a wide range of reference clock frequencies and lane operating frequencies, differential reference clock inputs that are selectively sourced from dedicated pins or internal ASIC interface pins, direct register control for all PMA functions, as well as a flexible layout to support placement along all edges in an ASIC.

Interested in learning more about our 56 Gbps multi-protocol SerDes PHY? You can check out our product page here and download our product brief here.

ZDNet journalist Cho Mu-Hyun reports that Samsung has confirmed a successful network processor tape-out based on the company’s 14LPP (Low-Power Plus) process technology in close collaboration with eSilicon and Rambus.

“[Samsung] used its 14 Low-Power Plus process and know-how from network applications together with eSilicon’s ASIC and 2.5D design capability and Rambus’ 28G SerDes solution for the design pattern,” writes Cho Mu-Hyun.

“Samsung also named its newly-developed 2.5 dimension turnkey solution I-Cube (Interposer-Cube), that connects a logic chip, or processor, with a HBM2 memory.”

As Mu-Hyun notes, the South Korean chip giant said the I-Cube solution will be essential to network applications for high-speed signaling in networks and will likely be adopted for other areas such as computing, servers and artificial intelligence – all areas where high-speed processing power is required.

“Samsung began applying the second-generation 14-nanometer process early last year for mobile chips,” Mu-Hyun explains. “The company has applied the 14-nanometer FinFET process for its own Exynos-brand of application processors, as well as for customers such as Qualcomm for its Snapdragon series.”

According to Ryan Lee, VP of Foundry Marketing at Samsung Electronics, Samsung’s 14LPP process technology, based on 3D FinFET structure, has already been proven for its high performance and manufacturability through mass production track record. The next generation process for network applications is 10LPP (Low-Power Plus) process which is based on 10LPE (Low-Power Early) that moved into mass production last year for the first time in the industry. 10LPP process’ mass production will be started in the second half of 2017.

“[Samsung] has begun mass production using its successor, the 10-nanometer process, for its upcoming Galaxy S8 smartphone. It started mass production of Exynos 9 using the process, which will power the phone,” ZDNet’s Mu-Hyun elaborates. “Qualcomm’s Snapdragon 835 is also being made using the cutting-edge process. These are being made using the 10 Lower-Power Early (10LPE) process before being upgraded to 10 Lower-Power Plus (10LPP), the second-generation, later this year. 10LPP will then be used for network processors as well.”

As Luc Seraphin, senior VP and general manager of Rambus Memory and Interfaces Division, tells Rambus Press, networking OEMs are looking for high-quality leadership IP suppliers that can bring 28G backplane SerDes in advanced FinFET process nodes to market.

“Our success with Samsung and eSilicon is a testament that these industry-leading solutions are attainable when you bring leading companies together. This is the first of several other offerings we plan to bring to networking and enterprise ASIC markets around the globe,” he adds.

Interested in learning more about Rambus’ 28G SerDes solution? You can check out our product page here.