SerDes PHYs

Semiconductor Engineering’s Ed Sperling recently penned an article about the challenges of IP reuse. The basic business proposition for third-party IP, says Sperling, is that it’s cheaper, faster and less problematic to buy rather than build.

[“However], things haven’t exactly worked out according to plan, either for companies that license IP or those that develop it,” he explained.

“For IP licensees, just keeping track of an endless series of updates is becoming unwieldy. Complex designs often include multiple builds of dozens of IP blocks, particularly at advanced process nodes.”

IP developers also face their own set of challenges, he emphasizes, as the demand for more customized IP transforms the business from “write-once, use everywhere,” to “write once, modify every time.” Even in cases where the IP is relatively fixed (such as processor cores), says Sperling, customers may require extensive system optimization tweaks.

To further complicate matters, every new rev of a process technology at advanced nodes requires changes to the IP. Designing at 10/7nm is particularly difficult because the process and the IP are in almost constant flux. Nevertheless, even at older nodes the advent of new processes to address new or existing markets have made it more difficult for IP vendors to stay current.

Commenting on the above, Frank Ferro, senior director of product management at Rambus, told Semiconductor Engineering that OEMs once shed ASIC teams in favor of buying commodity IP and chips.

“[This] made it a lot harder for these companies to differentiate themselves. Now companies are hiring back ASIC teams and doing a mixed model,” said Ferro. “They do IP development where it makes sense and add customization. But even with standard IP, they add a little differentiation to make it a little better.”

Nevertheless, says Ferro, the goal is still to build IP and license it to at least 10 customers.

“We’ve been in the custom business because of the nature of hard IP, which means we work with the foundries to develop that IP. But even if it’s off-the-shelf, there are little differences from one design to the next,” he continued. “So even if it’s a stable architecture like 28 [gigabits per second] SerDes, which is a known design, you might only be able to re-use a portion of that because it’s very process-dependent. For 28 SerDes, you have a version to use with PCIe, with PONs (passive optical networks) and with short-reach – and you do that because you don’t want to pay the power and area penalty for re-using the same IP. That happens with automotive IP, too.”

Interested in learning more about the challenges of IP reuse? The full text of “The Limits of IP Reuse” by Ed Sperling can be read here on Semiconductor Engineering.

Juniper Research analysts forecast that wireless VR headsets (smartphone-based and standalone) data consumption will increase by over 650% over the next 4 years, from nearly 2,800PB (Petabytes) in 2017 to over 21,000PB in 2021. Moreover, when combined with traffic generated by VR headsets tethered to PCs and consoles, data consumption is expected to reach over 28,000PB, placing additional strain on both wired and wireless networks.

“VR requires fast data speeds to stream content effectively and, by 2021, the data demand of each VR device is expected to exceed that of 4K,” Juniper analysts stated in an August 2017 press release.

“This will be driven by the need for higher image quality and frame rates, a developing problem as VR becomes more mainstream.”

According to Juniper analyst James Moar, author of “Virtual Reality Markets: Hardware, Content & Accessories 2017-2022,” social VR is also on the rise, with Facebook and WeChat developing VR platforms and several VR games such as Star Trek: Bridge Crew.

“VR is currently seen as very isolating,” Moar explained. “The promise of having new worlds to explore is much more compelling when other people can share the experience, which needs social games and social interfaces, as well as the development of cross-platform standards.”

In related news, Sam Rosen, Managing Director and VP at ABI Research, recently observed that 360-degree content has already been tested in major genres including sports (such as BT’s distribution of the Champion’s League), music (Deutsche Telekom’s Magenta Musik service), and news (New York Times VR). In addition, Netflix launched its first interactive content with children’s programs Puss in Boots and Buddy Thunderstruck.

“Immersive content promises to marry Hollywood style content, tapping into the production elements of video games,” said Rosen. “New technologies exist to conduct fully spatial and/or light field mapping of spaces, as well as to generate holographic models of actors. Combining these techniques with artist-generated layers and interactive storytelling elements, such as speech synthesis, opens the door to using gaming technologies to deliver immersive entertainment to large audiences.”

Rosen also noted that 360-degree video faces a variety of filming and distribution challenges, including stitching, algorithms and workflows that vary widely between live and file-based scenarios. Delivering the full panorama to the user, says the analyst, requires about 4-5 times the displayed resolution, depending on the field of view of the headset.  However, attempting to deliver only the required video requires low latency (delivery) – which places artificial limitations on head movement (in degrees per minute) or results in extreme pixilation of images.

“The 360-degree video market presents a struggle for content creators – on the one hand the new technology enables them to tell stories in a more impactful and immersive way, but it also requires new expertise, workflows and hardware,” he added.

According to Qualcomm, VR and AR are poised to be ideal applications for upcoming 5th generation (5G) mobile networks, as both will benefit from enhanced mobile broadband with its higher capacity, more uniform experience with consistently high data rates and lower latency.

“The AR and VR industry is thirsty for the capabilities 5G promises. It is a profound change in the way cellular networks have traditionally been developed: if you build it (the network), they will come (applications and users),” Qualcomm explained in a blog post earlier this year. “While we expect 5G to enable many new and unforeseen use cases, the enhanced capabilities of 5G are required for AR and VR to reach their full potential.”

As we’ve previously discussed on Rambus Press, the move from 4G to 5G is driving new architectures such as C-RAN, which further pushes SerDes requirements to communicate between remote radio head (RRH) and baseband unit (BBU) from 12G to as high as 48G. From a broader perspective, our increasingly connected world is prompting the semiconductor industry to implement and implement and innovate new architectures in the data center. These include DDR4 and DDR5 buffer chips, second-generation high bandwidth memory (HBM2) and hybrid DIMM technologies such as NVDIMM-P and NVDIMM-N.

Mohit Gupta, a senior director of product marketing for Rambus’ Memory and Interfaces Division, has penned an article for Semiconductor Engineering about the growing industry interest in SoC/ASIC disaggregation.

As Gupta notes, petabytes of data are continuously generated by a wide range of devices, systems and IoT endpoints such as vehicles, wearables, smartphones and even appliances. The resulting digital tsunami has prompted industry heavyweights like Google, Microsoft, Facebook and Amazon to consider implementing and innovating new architectures in the data center to remove bottlenecks.

“After years of steady SoC/ASIC aggregation, a disaggregated approach is now seriously being considered in the form of SerDes chiplets and specialized low-power, application-specific die-to-die interfaces,” he explained. “The concept of SoC/ASIC disaggregation is certainly timely, as demands for higher bandwidth within a similar power envelope will only increase.”

According to Gupta, designing silicon on more advanced process nodes is clearly one option, although the costs at 7nm and beyond are quite high. Moreover, developing mixed-signal silicon on consecutive nodes is both challenging and expensive. To further complicate matters, SoC designs are fast approaching the outer limits of both yield capabilities and reticle size architecture.

“However, die-to-die interfaces can more easily accommodate multiple applications across memory, logic and analog technology,” he stated. “In addition, die-to-die interfaces do not require a matching line/baud rate and number of lanes. Moreover, forwarded clock architecture provides a low power solution, while FEC may or may not be required depending upon latency requirements.”

A number of companies, says Gupta, are already actively pursuing SoC/ASIC aggregation for switches and other systems. Similarly, the industry is developing ASICs with die-to-die interfaces on leading FinFET nodes, while at least one next-generation server chip is being designed with disaggregated IOs on a separate die.

“Understanding the advantages of SoC/ASIC disaggregation can help the semiconductor industry evolve on both a micro (silicon) and macro level (data center). With SoC designs fast approaching the outer limits of both yield capabilities and reticle size architecture, the concept of disaggregation has never been timelier,” he concluded.

Rambus is attending the Samsung Foundry Forum at the Santa Clara Marriott on May 24^th. The company will be showcasing its 56G SerDes PHY, which is being developed on Samsung’s 10nm LPP (Low-Power Plus) process technology.

As we’ve previously discussed on Rambus Press, our 56G SerDes PHY supports PAM-4 and NRZ signaling and data rates from 9.95Gbps to 58Gbps across copper and backplane channels with more than 35dB insertion loss. At the heart of the SerDes architecture is an ADC (analog to digital converter) operating at 28 GS/s that allows for adjustable power consumption and improved performance while providing low BER (Bit Error Rate) for enterprise class reliability.

Key product highlights include an analog Rx CTLE with combined 12 dB of peaking gain, digital Tx/Rx FFE and DFE, support for Ethernet auto negotiation and multiple lane configurations to facilitate flexible ASIC floorplan integration. The 56G MPS also offers BIST with PRBS generators and checkers, extensive debug capabilities and interfaces using an internal microprocessor, as well as LabStation™ software and scripts for enhanced bring-up and validation.

Additional features include support for up to 8 duplex Lanes and data rates in the range of 9.95 Gbps – 58 Gbps, RX front end with on-chip capacitors to support both AC-coupled and DC-coupled channels, configurable architecture that enables power saving models for low and medium loss channels, as well as a flexible ASIC interface for sharing impedance codes amongst multiple PMAs and reducing the number of external reference resistors for on-chip impedance calibration.

The 56G MPS also offers programmable TX/RX equalizers, a centralized LC-PLL that supports a wide range of reference clock frequencies and lane operating frequencies, differential reference clock inputs that are selectively sourced from dedicated pins or internal ASIC interface pins, direct register control for all PMA functions, as well as a flexible layout to support placement along all edges in an ASIC.

Interested in learning more about our 56 Gbps multi-protocol SerDes PHY? You can check out our product page here and download our product brief here.

Mohit Gupta, senior director of product marketing for Rambus’ Memory and Interfaces Division, recently penned an article for Semiconductor Engineering that explores the connection between SerDes and terabit Ethernet.

According to Gupta, 400 Gigabit Ethernet (400GbE) and 200 Gigabit Ethernet (200GbE) are currently slated for official release by the IEEE P802.3cd Task Force in December 2017.

“Although there is not yet an official IEEE roadmap detailing what lies beyond 400GbE, doubling to 800GbE will likely become a reality when single-lane 112Gbps links hits the market,” he explained. “This technology will allow for larger lane bundles, providing 1 TbE or 1.6 TbE link with 10 or 16 lanes, respectively.”

As Gupta notes, Amazon, Facebook and Google are moving to 100GbE connections in 2017 and are expected to begin purchasing 400GbE systems by 2019.

“It is therefore important for the current generation of 56Gbps SerDes PHYs to meet the long-reach backplane requirements for the industry transition to 400GbE Ethernet applications,” he stated. “This allows the SerDes PHY to scale to speeds as fast as 112Gbps, which are required in the networking and enterprise segments, such as enterprise server racks that are moving from 100GbE to 400GbE and beyond.”

Ethernet is clearly moving faster than ever, due to the rise of Big Data, the Internet of Things (IoT) and other trends that place increasingly high demands on communication channels. In fact, there is already a forum for 112Gbps SerDes which will be critical in driving the 800GbE standard forward. Supporting faster Ethernet speeds, says Gupta, presents a distinct set of challenges for SerDes designers. In addition to maintaining signal integrity, engineers must contend with a stringent set of design requirements, such as architecting next-generation silicon within the same power envelope – without the support of Dennard Scaling.

“Although lower process nodes facilitated by Moore’s Law are obviously beneficial, there are numerous design tradeoffs, specifically around area and power, that should be carefully considered,” he continued. “To be sure, one of the biggest costs involved in running a data center is electricity consumption, so there has always been a significant emphasis on keeping the power low for such links – even though they are targeted for higher speeds.”

According to Gupta, the ideal paradigm for a high-speed, next-generation SerDes that supports Terabit Ethernet is one that maximizes performance with the lowest power draw and smallest area. However, a more realistic scenario would see compromises on performance, power and area, with trade-offs based on specific product requirements.

For example, he says, engineers may want to consider designing a lower reach SerDes that is cheaper on power/area and uses additional components on board such as re-timers to stay within the same budget. In addition, the channel can be made smooth enough to take off some SerDes equalization to maximize power and area efficiency. Moreover, extra PLL/VCO’s can be eliminated, while the merits and extent of backwards compatibility should be assessed.

“Ethernet speeds are fast approaching 800GbE and beyond. Since SerDes PHYs will be playing an important part in the development of terabit Ethernet, system architects should carefully consider the pros and cons of design tradeoffs around area and power. Deciding on a specific set of tradeoffs for high-speed serial links may very well be one of the most stressful parts of the entire design process, although it is critical for maximizing operational efficiency at 400 GbE and beyond,” he concluded.

Rambus is currently collaborating with PLDA and Avery Design Systems Inc. to offer a comprehensive, silicon-proven PCI Express (PCIe) 4.0 solution, with backward compatibility to PCIe 3.0 and 2.0. According to Bill Fuller, a senior director of field application engineering at Rambus, the new PCIe sub-system includes the Rambus SerDes PHY, the PLDA PCIe controller and Avery Design’s verification IP. The solution is pre-verified and validated for simple integration into application-specific integrated circuits (ASICs).

“Our collaboration with PLDA and Avery Design offers customers a complete, pre-verified PCIe sub-system, with silicon-proven SerDes and a PCIe controller,” said Fuller. “Our line-up of SerDes PHYs is optimized for power and efficiency, delivering maximum performance and flexibility for today’s most challenging systems for a variety of applications including networking, data center and high-performance computing.”

As Fuller notes, the Rambus PCIe 4.0 PHY IP, which seamlessly connects to PIPE 4.2-compliant third-party controllers, is a low-power, area-optimized and silicon-proven IP designed with a system-oriented approach to facilitate easy integration and maximize flexibility. The PHY IP consists of a hard Physical Media Attachment (PMA) designed with a minimal set of broadside control and status pins, as well as a soft-configurable Physical Coding Sublayer (PCS), to support a wide range of applications. These include storage and memory connectivity, hybrid storage systems, server connectivity, as well as ASIC, FPGA and GPU interfacing.

“The PHYs have a minimal set of broadside control and are configurable in x2, x4 and x8 lane configurations. This gives the PHYs improved flexibility and support for a wide range of applications. The PCIe 4.0 PHYs are also rigorously tested through third party compliance testing and internal interoperability system testing,” Fuller explained. “Moreover,

to improve system margin and performance, our solution features transmit and receive equalization and full equalization adaptation. This ensures that data is recovered even in the presence of channel and system interference.”

Additional features include:

• Automatic calibration of key circuits to maximize performance and yields
• In-situ real-time monitoring and receive data eye schmo
• Flexible ASIC clocking
• Tight skew control of 2UI between lanes of the PMA
• 3-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
• Deterministic latency within +-1UI variation for Tx lane
• Continuous time linear equalizer (CTLE) with programmable settings providing up to 12dB gain peaking at Nyqvist frequencies
• 6-tap Rx DFE (decision feedback equalizer)
• Second-order CDR meeting SSC and RX sinusoidal jitter requirements
• Expandable register interface enabling communication with multiple PMAs and PCS-BIST soft macros
• Built-in Self Test (BIST) with ATPG and AC/DC Boundary scan support
• Built-in PRBS pattern generation and checking for standalone loopback testing
• Operation across a wide temperature range (-40 C to +125 )
• Support for bifurcation and quadfurcation modes
• Includes ESD structures
• SRIS support

Rambus’ PCIe 4 SerDes PHYs are available on TSMC, Global Foundry and Samsung process nodes. For additional information, please visit our PCIe 4 SerDes PHY product page on Rambus.com here.