Rambus has announced a comprehensive interface solution for PCI Express 5 (PCIe 5.0) consisting of a new PCIe 5.0 PHY and a co-verified Northwest Logic Expresso 5.0 controller.
“Our high-speed SerDes and memory interface solutions make possible amazing advancements in performance-intensive applications in AI, data center, HPC, storage and networking,” said Hemant Dhulla, VP and GM of IP Cores. “Now we’ve added PCIe 5 to our industry-leading portfolio of high-speed interface solutions giving chip makers another tool to unleash the power of their designs.”
With co-verified PHY and controller, Rambus greatly reduces integration complexity for chip designers. Both PHY and controller support PCI Express 5 and are backward compatible to PCIe 4.0, 3.0 and 2.0. While together they are an ideal complete solution, both PHY and controller can be paired with PIPE 5.2 – compliant 3rd-party solutions if so desired.
In addition to PCI Express 5, the Rambus PHY supports the Compute Express Link (CXL) connectivity standard. CXL is a new high-speed interconnect between CPUs and workload accelerators or other attached devices, as well as CPUs and memory. It maintains memory coherency between the CPU and attached devices. This greatly benefits accelerators used to complement CPUs in applications such as artificial intelligence and machine learning.
This latest portfolio addition highlights Rambus leadership in high-speed SerDes PHY and controller IP, leveraging the company’s long tradition of signal and power integrity expertise coupled with the design talent and products from newly acquired Northwest Logic.
Keep on reading: all the details on the PCI Express 5 interface solution