ZDNet journalist Cho Mu-Hyun reports that Samsung has confirmed a successful network processor tape-out based on the company’s 14LPP (Low-Power Plus) process technology in close collaboration with eSilicon and Rambus.
“[Samsung] used its 14 Low-Power Plus process and know-how from network applications together with eSilicon’s ASIC and 2.5D design capability and Rambus’ 28G SerDes solution for the design pattern,” writes Cho Mu-Hyun.
“Samsung also named its newly-developed 2.5 dimension turnkey solution I-Cube (Interposer-Cube), that connects a logic chip, or processor, with a HBM2 memory.”
As Mu-Hyun notes, the South Korean chip giant said the I-Cube solution will be essential to network applications for high-speed signaling in networks and will likely be adopted for other areas such as computing, servers and artificial intelligence – all areas where high-speed processing power is required.
“Samsung began applying the second-generation 14-nanometer process early last year for mobile chips,” Mu-Hyun explains. “The company has applied the 14-nanometer FinFET process for its own Exynos-brand of application processors, as well as for customers such as Qualcomm for its Snapdragon series.”
According to Ryan Lee, VP of Foundry Marketing at Samsung Electronics, Samsung’s 14LPP process technology, based on 3D FinFET structure, has already been proven for its high performance and manufacturability through mass production track record. The next generation process for network applications is 10LPP (Low-Power Plus) process which is based on 10LPE (Low-Power Early) that moved into mass production last year for the first time in the industry. 10LPP process’ mass production will be started in the second half of 2017.
“[Samsung] has begun mass production using its successor, the 10-nanometer process, for its upcoming Galaxy S8 smartphone. It started mass production of Exynos 9 using the process, which will power the phone,” ZDNet’s Mu-Hyun elaborates. “Qualcomm’s Snapdragon 835 is also being made using the cutting-edge process. These are being made using the 10 Lower-Power Early (10LPE) process before being upgraded to 10 Lower-Power Plus (10LPP), the second-generation, later this year. 10LPP will then be used for network processors as well.”
As Luc Seraphin, senior VP and general manager of Rambus Memory and Interfaces Division, tells Rambus Press, networking OEMs are looking for high-quality leadership IP suppliers that can bring 28G backplane SerDes in advanced FinFET process nodes to market.
“Our success with Samsung and eSilicon is a testament that these industry-leading solutions are attainable when you bring leading companies together. This is the first of several other offerings we plan to bring to networking and enterprise ASIC markets around the globe,” he adds.
Interested in learning more about Rambus’ 28G SerDes solution? You can check out our product page here.