Next-gen Rambus RISC-V security products
According to Bret Sewell, SVP and general manager of the Rambus Security Division, Codasip Studio provides fully automated generation of the Software Design Kit (SDK) for RISC-V processors. More specifically, Codasip Studio utilizes a high-level design flow based on a proprietary modeling language known as “CodAL” that significantly reduces the amount of engineering time and resources required to create, verify and validate SDKs for embedded processors.
“Security is the leading issue for IoT, automotive and other fast-growing markets and it is critical for Rambus to deliver superior products to market in a timely fashion,” says Sewell. “We selected Codasip Studio as a high-level design tool for SDK generation because it allows for fast design space exploration – and because of the high quality of results we are realizing in the automatically generated compiler toolchain.”
A closer look at Codasip
As Karel Masařík, co-founder and CEO of Codasip explains in a recent press release, capabilities of the RISC-V embedded processor only need to be described once in the CodAL high-level language. From this single description, everything required to design, integrate and program the embedded processor is automatically derived. This effectively eliminates the need to express the same functionality in multiple task dependent formats and traditional manual tasks.
In addition to its processor design capabilities, Codasip Studio offers powerful debugging and profiling – which makes even the most complex embedded processor designs easy to manage.
Key features of Codasip Studio include:
- Powerful Eclipse-based IDE
- Support for leading open source tools and standards
- Algorithm to implementation design flow
- Automatic generation of complete ASIP toolchain
- Advanced profiling tools
- End-to-end multiprocessor-aware debug
- Multi-core SDK management
Rambus, RISC-V and SiFive
We joined the RISC-V Foundation as a founding member in April 2016. As we’ve previously discussed on Rambus Press, RISC-V is an instruction set architecture designed as an open standard. Based on years of research conducted at the University of California, Berkeley, the RISC-V standard is designed to be open and flexible, supporting a wide variety of academic and industry use cases. By embracing standards such as RISC-V, the semiconductor industry can find new efficiencies and revenue opportunities – while creating an ecosystem that is favorable to developers and manufacturers.
In August 2017, we confirmed a collaborative partnership with SiFive, which offers licensable CPUs from the inventors of RISC‑V. More specifically, our security technology will be made available for use with SiFive’s Freedom platforms. This includes a hardware root-of-trust, cryptographic cores, key provisioning capabilities and high-value services that are enabled by design. According to Martin Scott, Senior Vice President and General Manager of Rambus’ Security Division, the two companies share a similar philosophy of easing the path to designing innovative and cost-effective SoCs.
“SiFive and Rambus [are partnering] with an intent of providing chip-to-cloud-to-crowd security solutions that easily integrate with the SiFive Freedom platform and support the open and growing RISC-V hardware ecosystem. Our security cores, embedded in Freedom Platform SoCs will enable secure in-field device connection and attestation for updates and diagnostics,” he adds.