Our On-Chip Power Supply Noise Monitor has been developed to overcome the characterization challenges of low-power, high-performance interfaces and electronic systems. It is a compact IP block embedded on-chip and works in conjunction with our LabStation™ Validation Platform to enable noise measurements directly on the chip.
Briefs
LabStation Validation Platform Product Brief
Design complexity for advanced SoCs rises with each new process node, performance increase, and addition of new IP blocks. Designers are faced with increasing challenges to confidently verify and validate functionality of their chips. The LabStation Validation platform is a comprehensive tool suite for the rapid bring-up, validation and characterization of complex low-power, high-performance memory and serial link IP. It is designed to be easy to use and improve productivity while providing improved accuracy of test results and confidence is system performance.
LPDDR3 DRAM Product Brief
Download “LPDDR3 DRAM Product Brief”
The LPDDR3 DRAM brings next-generation, low-power DRAM performance to the market today. The Rambus enhanced LPDDR3 DRAM is a natural extension to the low power family of DRAM. The LPDDR3 DRAM is optimized for mobile applications and is fully-compliant with industry LPDDR3e/ LPDDR3 specifications. When paired with an R+ LPDDR3 PHY, the DRAM supports data rates of up to 2133 Mbps, while providing an active power reduction of up to 30% when compared to a standards-only LPDDR3 device at equivalent speed. The improvement in power consumption is due in part to the use of Low Voltage Swing Terminated Logic (LVSTL) signaling technology that features a significantly reduced signal swing versus the 1.2 volt HSUL (High Speed Unterminated Logic) signal swing of LPDDR3. By supporting both signaling types, the LPDDR3 DRAM offers an enhanced performance, low-power mode while maintaining compliance with LPDDR3e and LPDDR3 standards and specifications.LPDDR3 PHY Product Brief
Fully compliant with LPDDR3 and LPDDR2 DRAM specifications, our LPDDR3 PHY pairs with the LPDDR3 DRAM to create a memory subsystem that supports data rates of up to 2133 Mbps, and reduces active memory system power by up to 25% and active DRAM power by up to 30%. This enables a significantly improved thermal profile and an increased battery life in the end device. The improved thermal profile also enables the memory system to run at peak bandwidth for longer periods of time, which translates to better overall performance in the end systems.
The improvement in power consumption is a result of Low Voltage Swing Terminated Logic (LVSTL), a single-ended, ground-terminated signaling technology, used while in R+ mode. LVSTL features a significantly reduced signal swing versus the 1.2 volt HSUL (High Speed Unterminated Logic) signal swing of standard LPDDR3. Reduced signal swing translates to significantly reduced IO power at high data rate, which is a major component of DRAM power. By supporting LVSTL and HSUL signaling, LPDDR3 offers a low-power mode while maintaining compatibility with LPDDR3 and LPDDR2 DRAM standards.
