At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
The Rambus PCI Express® (PCIe®) 6.0 PHY is a low-power, area-optimized, silicon IP core designed with a system-oriented approach to maximize flexibility and ease of integration. It delivers up to 64 GT/s signaling rates in performance-intensive applications for artificial intelligence (AI), data center, edge, networking, and HPC.
The PCIe 6.0 PHY can be combined with the Rambus PCIe 6.0 controller core to make a complete PCIe 6.0 interface subsystem.
The PHY is configurable in x1, x2, x4, x8 and x16 lane configurations with bifurcation support. This gives the PHY improved flexibility and support for a wide range of applications. Multi-tap transmitter and adaptive receiver equalization supports more than 36dB of channel insertion loss. The PHY also supports the latest version of the Compute Express Link™ (CXL™) specification, version 3.0, enabling new use models for data center architectures.
The PCIe 6 SerDes PHY is available on advanced process nodes.
The PCIe interface is the critical backbone that moves data at high bandwidth and low latency between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. With the torrid rise in bandwidth demands of advanced workloads such as AI/ML training, PCIe 6.0 jumps signaling to 64 GT/s with some of the biggest changes yet in the standard.
|Protocol||Signaling Rate (GT/s)||Application|
|PCIe 3.1/3.0||8||Servers, storage, networking devices|
|PCIe 4.0||16||Servers, storage, networking devices|
|PCIe 5.0||32||AI, servers, storage, networking, 5G infrastructure|
|PCIe 6.0||64||AI, servers, storage, networking, 5G infrastructure|
Maintaining signal integrity has become increasingly difficult as data rates moves past 28Gbps to 56Gbps and beyond. Up to 28Gbps rates, NRZ is the preferred and standardized encoding scheme which consists of 1’s and 0’s. NRZ is also referred to as PAM2 (pulse amplitude modulation, 2-level), due to its two amplitude levels which contain 1 bit of information in every symbol. With serial data rates hitting 56 Gb/s per channel, signal impairments caused by increased bandwidth has prompted the high-speed serial data industry to adopt PAM4, or 4-level pulse amplitude modulation.