The PHYs come complete with a PMA hard macro that supports PCIe 4.0, 3.0, and 2.0 protocols and a physical coding sublayer (PCS) soft macro for PCIe that is PIPE4.2 compliant. They have a minimal set of broadside control and are configurable in x2, x4 and x8 lane configurations. This gives the PHYs improved flexibility and support for a wide range of applications. The PCIe 4.0 PHYs are rigorously tested through third party compliance testing and internal interoperability system testing.
In order to improve system margin and performance, our solution features transmit and receive equalization and full equalization adaptation. This ensures that data is recovered even in the presence of channel and system interference.
Our PCIe 4 SerDes PHYs are available on TSMC, Global Foundry and Samsung process nodes.