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Building A Defense In Depth Against Cyberattacks

Building A Defense In Depth Against Cyberattacks

As the number and type of cyberattacks, from the “simple and cheap” to the “expensive and sophisticated,” continues to grow at a dramatic pace, protection of chips and devices must employ a defense in depth strategy. In this way, if an attacker successfully bypasses a mechanism of protection, they’ll face another layer of defense, rather than a clear path to the assets they seek to exploit. In this blog, we’ll talk about some of the protections security architects can marshal to build a defense in depth.

Power Grids Under Attack

Cyberattacks are becoming as troublesome to the electrical power grid as natural disasters, and the problem is growing worse as these grids become more connected and smarter. Unlike in the past, when a power outage affected just the electricity supplied to homes and businesses, power grids are becoming core elements of smart cities, infrastructure, and safety-related services. Without power, none of this works, and sophisticated cybercriminal operations can hold large regions hostage until they pay enormous ransoms or give into other demands.

CXL™ Consortium Member Spotlight: Rambus

CXL™ Consortium member company Rambus participated in a recent Q&A session to discuss CXL’s impact on the evolution of the data center, Rambus’ expertise in CXL interface subsystems, and ideal use cases for CXL technology. Find the full Q&A session with Rambus below.

Rambus Delivers PCIe 6.0 Controller for Next-Generation Data Centers

Highlights:

  • Pushes performance to 64 GT/s for advanced AI/ML, storage and networking applications
  • Implements full PCIe 6.0 feature set with optimized power, area and latency
  • Offers state-of-the-art data security with integrated IDE engine
Rambus PCIe 6.0 Controller Block Diagram
Rambus PCIe 6.0 Controller Block Diagram

SAN JOSE, Calif. – Jan. 26, 2022 – Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced the availability of its PCI Express® (PCIe®) 6.0 Controller. The PCIe specification is the interconnect of choice across a broad landscape of data-intensive markets including data center, AI/ML, HPC, automotive, IoT, defense and aerospace. Optimized for power, area and latency, the Rambus PCIe 6.0 controller delivers data rates up to 64 Gigatransfers per second (GT/s) for high-performance applications. In addition, the controller provides state-of-the-art security with an Integrity and Data Encryption (IDE) engine that monitors and protects PCIe links against physical attacks.

“The rapid advancement of AI/ML and data-intensive workloads requires that we continue to provide higher data rate solutions with best-in-class latency, power and area,” said Sean Fan, chief operating officer at Rambus. “As the latest addition to our portfolio of industry-leading interface IP, our PCIe 6.0 Controller offers customers an easy to integrate solution that delivers both performance and security for advanced SoCs and FPGAs.”

Key features of the Rambus PCIe 6.0 Controller include:

  • Supports PCIe 6.0 specification including 64 GT/s data rate and PAM4 signaling
  • Supports fixed-sized FLITs that enable high-bandwidth efficiency
  • Implements low-latency Forward Error Correction (FEC) for link robustness
  • Internal data path size automatically scales up or down based on max. link speed and width for reduced gate count and optimal throughput
  • Backward compatible to PCIe 5.0, 4.0 and 3.0/3.1
  • Supports Endpoint, Root-Port, Dual-Mode and Switch port configurations
  • Integrated IDE optimized for performance

More Information:
For more information on the PCIe 6.0 Controller, please visit our website. Or, view the PCIe 6.0 specification online.

CXL emerges as memory coherent fabric leader as GenZ Consortium transfers assets

In this 451 Research analysis, the report describes Compute Express Link Consortium’s acquisition of Gen-Z Consortium, seeking “to establish cache-coherent interconnects for processors, memory expansion and accelerators.” Read how this consolidation could positively affect both memory semantic protocols that enable high-speed connectivity to processors, accelerators and memory expansion technologies and the overall market.

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