Part of a full suite of memory controller add-on cores, the Error Correction Coding (ECC) core implements the standard Hamming Code-based DRAM Single Error Correction (SEC) and Double Error Detection (DED) algorithms. The Read-Modify-Write core, offered separately, can be used in conjunction with the ECC Core when dealing with misaligned bursts.
ECC Core Product Brief
PCIe 4.0 Controller Product Brief
The PLDA PCIe 4.0 Controller is designed to achieve maximum PCI Express (PCIe) 4.0 performance with great design flexibility and ease of integration. It comprises a complete SerDes subsystems with the Rambus PCIe 4.0 PHY or can integrate with PIPE 4.2-compliant 3rd-party PHYs. The controller is backwards compatible with PCIe 3.1/3.0.
MIPI Testbench Product Brief
The Northwest Logic MIPI Testbench emulates a MIPI device enabling end-to-end simulation of a MIPI design. It includes separate versions for CSI-2 Transmit, CSI-2 Receive, DSI-2 Host (Transmit), DSI-2 Peripheral (Receive), DSI Host, and DSI Peripheral.
CSI-2 Controller Product Brief
The Northwest Logic CSI-2 controller core is a second-generation MIPI CSI-2 core optimized for high performance, low power and small size. The core is fully compliant with the CSI-2 standard and implements all three layers defined therein: Pixel to Byte Packing, Low Level Protocol, and Lane Management.
DSI-2 Controller Product Brief
The Northwest Logic DSI-2 controller core is a second-generation MIPI DSI core optimized for high performance, low power and small size. The core is fully compliant with the DSI-2 standard and implements all three layers defined therein: Pixel to Byte Packing, Low Level Protocol, and Lane Management.
Multi-Protocol Engines Brochure
Multi-Protocol Engine IPs offer acceleration of IPsec, MACsec, SSL/TLS/DTLS, sRTP and basic hash-crypto in architectures ranging from the look-aside engines to the more sophisticated, powerful inline packet engines.
