At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
Found 20 Results
High-Performance Memory for AI/ML and HPC: Part 2
https://www.rambus.com/blogs/high-performance-memory-for-ai-ml-and-hpc-part-2/In part one of this two-part series, Semiconductor Engineering Editor in Chief Ed Sperling and Rambus Sr. Director of Product Management Frank Ferro took a closer look at the various types of memory that system designers are using to support artificial intelligence (AI), machine learning (ML), and high-performance computing (HPC) applications. In this blog post, […]
eSilicon Tapes Out 7nm Combo PHY (HBM2/HBM2E/Low Latency) Test Chip
https://www.rambus.com/esilicon_combo_phy_hbm2_hbm2e_low_latency/Chip facilitates continued support of the latest HBM technologies for eSilicon’s 2.5D FinFET ASICs SAN JOSE, Calif. — May 9, 2019 — eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today the tapeout of a 7nm test chip to provide silicon validation of its physical interface (PHY) […]
Rambus 112G SerDes PHY Article in eeweb.com/EE Times
https://www.rambus.com/blogs/rambus-112g-serdes-phy-article-in-eeweb-com-ee-times/Ken Dyer, Director, Engineering Architecture, is the author of a 112G Long Reach (LR) SerDes PHY article in eeweb.com/EE Times network. The 112G is coming on to the market to comply with growing demands for greater bandwidth for next generation data centers as well as for advanced applications like artificial intelligence (AI) and machine learning, […]
112G LR SerDes PHY Ready for Next-Gen Networking Gear
https://www.rambus.com/blogs/112gbps-lr-serdes-phy-ready-for-nexgen-networking-gear/Rambus has officially announced the 112G Long Reach (LR) SerDes PHY. Hemant Dhulla, VP and GM of IP Cores, said, “By leveraging leading 7nm process technology, Rambus is enabling the next generation of communications and data center applications.” He further stated, “We’re excited to continue to expand our IP portfolio and deliver our customers top-of-the-line performance […]
Rambus Announces Tapeout and Availability of 112G Long Reach SerDes PHY on Leading-edge 7nm Node for High-Performance Communications and Data Centers
https://www.rambus.com/rambus-announces-tapeout-and-availability-of-112g-long-reach-serdes-phy/SerDes PHY delivers leading-edge performance and power efficiency for next-generation SoCs in data-intensive applications Rambus 112G Long Reach SerDes PHY Rambus Modeled PAM-4 Signaling Transmit Eye SUNNYVALE, Calif. – April 16, 2019 – Today Rambus Inc. (NASDAQ: RMBS) announced its newest portfolio solution of 112G Long Reach (LR) SerDes PHY on a leading-edge 7nm process node for next-generation […]
Rambus Reports Fourth Quarter and Fiscal Year 2017 Financial Results
https://www.rambus.com/fourth-quarter-year-2017-financial-results/Annual revenue of $393.1 million, up 17% year over year; fourth quarter revenue of $101.9 million, up 4% year over year Fourth quarter GAAP diluted net loss per share of $0.29; fourth quarter non-GAAP diluted net income per share of $0.19 Annual royalty revenue of $289.6 million and licensing billings of $289.6 million; fourth quarter […]
Let’s talk about 7nm
https://www.rambus.com/blogs/lets-talk-7nm/Frank Ferro, a senior director of product management at Rambus, recently penned an article for Semiconductor Engineering about the promises and challenges of 7 nanometers (nm). According to Ferro, the demand for 7nm is driving expected initial tape-outs from fabs by the end of 2017 – with initial volumes kicking off in 2018 and ramping […]
Rambus showcases 56G Multi-Protocol SerDes (MPS) PHY at the Samsung Foundry Forum
https://www.rambus.com/blogs/rambus-showcases-56g-multi-protocol-serdes-mps-phy-at-the-samsung-foundry-forum/Rambus is attending the Samsung Foundry Forum at the Santa Clara Marriott on May 24th. The company will be showcasing its 56G SerDes PHY, which is being developed on Samsung’s 10nm LPP (Low-Power Plus) process technology. As we’ve previously discussed on Rambus Press, our 56G SerDes PHY supports PAM-4 and NRZ signaling and data rates from […]
Understanding the SerDes – Terabit Ethernet connection
https://www.rambus.com/blogs/understanding-the-serdes-terabit-ethernet-connection/Mohit Gupta, senior director of product marketing for Rambus’ Memory and Interfaces Division, recently penned an article for Semiconductor Engineering that explores the connection between SerDes and terabit Ethernet. According to Gupta, 400 Gigabit Ethernet (400GbE) and 200 Gigabit Ethernet (200GbE) are currently slated for official release by the IEEE P802.3cd Task Force in December 2017. “Although there is not […]
TIRIAS Research analyzes Rambus’ memory and high-speed interfaces strategy
https://www.rambus.com/blogs/tirias-research-analyzes-rambus-memory-and-high-speed-interfaces-strategy/Jim McGregor, principal analyst at TIRIAS Research, recently spoke with Gary Hilson of the EE Times about Rambus’ 56G SerDes PHY. More specifically, the analog-to-digital converter (ADC) and (DSP) architecture of Rambus’ 56G SerDes PHY is designed meet the long-reach backplane requirements for the industry transition to 400 GB Ethernet applications. In practical terms, this […]
