At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
Found 298 Results
VESA Display Stream Compression (DSC): The Complete Guide
https://www.rambus.com/blogs/vesa-display-stream-compression-dsc-the-complete-guide/Learn everything you need to know about VESA Display Stream Compression (DSC), simply explained in our blog. Start reading! Display technology has advanced in leaps and bounds over the past decade. Electronics manufacturers have been using increasingly sophisticated display features as a way of differentiating their products in the highly competitive consumer electronics market. Each […]
Rambus Achieves PCI Express® (PCIe®) 5.0 Compliance for PCIe 5.0 Controller IP and Inspector PCIe 5.0 Interposer with Diagnostic IP
https://www.rambus.com/blogs/rambus-achieves-pci-express-pcie-5-0-compliance-for-pcie-5-0-controller-ip-and-inspector-pcie-5-0-interposer-with-diagnostic-ip/What products achieved PCIe 5.0 compliance? At the most recent PCI-SIG® Compliance Workshop held in Burlingame, CA, Rambus achieved PCIe 5.0 compliance for two products: PCIe 5.0 Controller IP, which is fully backward compatible to PCIe 4.0 and PCIe 3.1/3.0. It was certified at PCIe 5.0 x4 operating at 32 GT/s as an Endpoint controller […]
CXL Glossary
https://www.rambus.com/interface-ip/cxl-glossary/CXL Glossary A glossary of CXL IP terminology and relevant solutions. a | b | c | d | e | f | g | h | i | j | k | l | m | n | o | p | q | r | s | t | u | v | w […]
Improving I/O Performance and Reducing Costs with Single Root I/O Virtualization (SR-IOV)
https://www.rambus.com/blogs/improving-i-o-performance-and-reducing-costs-with-single-root-i-o-virtualization-sr-iov/While server virtualization is being widely deployed in an effort to reduce costs and optimize data center resource usage, an additional key area where virtualization has an opportunity to shine is in the area of I/O performance and its role in enabling more efficient application execution. Single Root I/O Virtualization (SR-IOV) provides a step forward […]
PCIe 6.0 Retimer Controller with CXL Support
https://www.rambus.com/interface-ip/pci-express/pcie6-retimer-controller/PCIe 6.0 Retimer Controller with CXL Support Contact Us PCI Express® (PCIe®) 6.0 links operating at 64 GT/s using PAM4 signaling have a reach of up to 13 inches at nominal conditions on standard PCBs. Extending trace routing beyond this distance results in higher first bit error rates (FBER) and reduced link efficiency due to […]
VESA DSC 1.2b Decoder for AMD Xilinx FPGAs Product Brief
https://go.rambus.com/vesa-dsc-1-2b-decoder-amd-xilinx-fpgas-product-brief#new_tabThe Rambus VESA® Display Stream Compression (DSC) decoder IP core for AMD Xilinx FPGAs deliver visually lossless video compression performance, enabling designers to handle the growing bandwidth requirements of cutting-edge displays with higher resolutions, faster refresh rates, and greater pixel depths.
VESA DSC 1.2b Decoder for Intel FPGAs Product Brief
https://go.rambus.com/vesa-dsc-1-2b-decoder-intel-fpgas-product-brief#new_tabThe Rambus VESA® Display Stream Compression (DSC) decoder IP core for Intel FPGAs deliver visually lossless video compression performance, enabling designers to handle the growing bandwidth requirements of cutting-edge displays with higher resolutions, faster refresh rates, and greater pixel depths.
VDC-M 1.2 Encoder for AMD Xilinx FPGAs Product Brief
https://go.rambus.com/vesa-vdc-m-1-2-encoder-amd-xilinx-fpgas-product-brief#new_tabThe Rambus VESA VDC-M 1.2 Encoder IP Core for AMD Xilinx FPGAs implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 decoder to deliver visually lossless video compression. The decoder supports various usage models, including typical MIPI Display Serial Interface 2 (MIPI DSI-2) usage models.
VDC-M 1.2 Encoder for Intel FPGAs Product Brief
https://go.rambus.com/vesa-vdc-m-1-2-encoder-intel-fpgas-product-brief#new_tabThe Rambus VESA VDC-M 1.2 Encoder IP Core for Intel FPGAs implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 decoder to deliver visually lossless video compression. The decoder supports various usage models, including typical MIPI Display Serial Interface 2 (MIPI DSI-2) usage models.
VESA DSC 1.2b Encoder for Intel FPGAs Product Brief
https://go.rambus.com/vesa-dsc-1-2b-encoder-intel-fpgas-product-brief#new_tabThe Rambus VESA® Display Stream Compression (DSC) encoder IP core for Intel FPGAs deliver visually lossless video compression performance, enabling designers to handle the growing bandwidth requirements of cutting-edge displays with higher resolutions, faster refresh rates, and greater pixel depths.
