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Found 286 Results
PCIe 5 Drill-Down with Rambus’ Suresh Andani: Part 1
https://www.rambus.com/blogs/pcie-5-drill-down-with-rambus-suresh-andani-part-1/Semiconductor Engineering Editor in Chief Ed Sperling recently sat down with Suresh Andani, Senior Director, Product Marketing and Business Development at Rambus, to discuss the evolution of PCIe and its latest iteration: PCIe 5. As Andani notes, PCIe 5 and subsequent iterations of the PCIe standard will continue to be one of the “key interfaces” […]
Side-Channel Attacks Target Machine Learning (ML) Models
https://www.rambus.com/blogs/side-channel-attacks-target-machine-learning-ml-models/Written by Paul Karazuba for Rambus Press A team of North Carolina State University researchers recently published a paper that highlights the vulnerability of machine learning (ML) models to side-channel attacks. Specifically, the team used power-based side-channel attacks to extract the secret weights of a Binarized Neural Network (BNN) in a highly-parallelized hardware implementation. “Physical […]
Anti-Tamper Cryptographic Cores
https://www.rambus.com/security/dpa-countermeasures/dpa-resistant-core/anti-tamper-cryptographic-cores/Security Anti-Tamper Cryptographic Cores Rambus DPA (Differential Power Analysis) Resistant Cryptographic hardware cores guard against the various side channel attacks that exploit unprotected cryptographic designs. Easily integrated into an ASIC or FPGA design, these cores resist tampering attacks attempting to obtain secret cryptographic key material through Differential Power Analysis (DPA), Differential Electromagnetic Analysis (DEMA) or […]
Memory Systems for AI: Part 6
https://www.rambus.com/blogs/memory-systems-for-ai-part-6/Written by Steven Woo for Rambus Press In part 5 of this series, we discussed the most common memory systems that are used in the highest performance AI applications. These include on-chip memory, high bandwidth memory (HBM) and Graphics DDR SDRAM (GDDR SDRAM). In this blog post, we’ll take an in-depth look at on-chip memory, […]
Controllers Newsletter – Q1 2020
https://www.rambus.com/controllers-newsletter-q1-2020/Looking Ahead to 2020 from Northwest Logic, now part of Rambus Northwest Logic is now part of Rambus Inc., a premier silicon IP and chip provider. We are now proud to offer comprehensive memory and SerDes IP solutions, including PHYs and controllers. We continue to offer standalone controllers, providing customers with the ability to get […]
Storage and Networking Bytes: PCIe5, OpenShift, and Veeam
https://www.datanami.com/2020/01/17/storage-and-networking-bytes-pcie5-openshift-and-veeam/#new_tabLet’s start with PCIe5, the spec for which was finalized in early 2019. Now manufacturers are now getting revved up to produce PCIe5 hardware in 2020, which will be a boon for data- and processor-hungry workloads like machine learning and AI, as well as high performance computing (HPC) workloads that rely on GPUS, FPGAs, and […]
Memory Test Analyzer Core Product Brief
https://go.rambus.com/memory-test-analyzer-core-product-brief#new_tabPart of a full suite of memory controller add-on cores, the Memory Test Analyzer Core can be used in conjunction with the Memory Test Core to capture actual and expected test data. The core is useful for chip and board validation. It provides low-cost, built-in logic analyzer capability similar in concept to FPGA-based internal logic […]
MIPI CSI-2 Controller Core
https://www.rambus.com/interface-ip/mipi/csi2-controller/MIPI CSI-2 Controller Core Contact Us The Rambus MIPI CSI-2 controller core is optimized for high performance, low power and small size. The core is fully compliant with the CSI-2 standard and implements all three layers defined therein: Pixel to Byte Packing, Low Level Protocol, and Lane Management. For automotive safety-critical applications, an ASIL-B version […]
PCIe 4.0 Controller
https://www.rambus.com/interface-ip/pci-express/pcie4-controller/PCIe 4.0 Controller Contact Us The PCIe 4.0 Controller (formerly XpressRICH) is designed to achieve maximum PCI Express® (PCIe®) 4.0 performance with great design flexibility and ease of integration. It is fully backward compatible with PCIe 3.1/3.0. A PCIe 4.0 Controller with AXI (formerly XpressRICH-AXI) is also available. The controller delivers high-bandwidth and low-latency connectivity for […]
DDR3 Controller
https://www.rambus.com/interface-ip/ddr/ddr3-controller/DDR3 Controller Contact Us The Rambus DDR3 controller core is designed for high memory throughput, high clock rates, and full programmability in computing and networking applications. Secure Site Login ContactProduct Brief How a DDR3 Interface Subsystem works The Rambus DDR3 controller maximizes memory bus efficiency via Look-Ahead command processing, bank management, auto-precharge and additive latency […]
