At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
Found 79 Results
GDDR6 Controller
https://www.rambus.com/interface-ip/gddr/gddr6-controller/GDDR6 Controller Contact Us The Rambus GDDR6 controller core is designed for use in applications requiring high memory throughput including graphics, advanced driver assistance systems (ADAS), data center and artificial intelligence (AI). Secure Site Login ContactProduct Brief How a 24G GDDR6 Memory Interface Subsystem works Originally designed for graphics applications, GDDR6 is a high-performance memory […]
Shattering the neural network memory wall with Checkmate
https://www.rambus.com/blogs/shattering-the-neural-network-memory-wall-with-checkmate/A recent paper published on arXiv by a team of UC Berkeley researchers observes that neural networks are increasingly bottlenecked and constrained by the limited capacity of on-device GPU memory. Indeed, deep learning is constantly testing the limits of memory capacity on neural network accelerators as neural networks train with high-resolution images, 3D point-clouds and […]
PCIe 5.0 Controller
https://www.rambus.com/interface-ip/pci-express/pcie5-controller/PCIe 5.0 Controller Contact Us The Rambus PCIe 5.0 Controller (formerly XpressRICH from PLDA) is designed to achieve maximum PCI Express® (PCIe®) 5.0 performance with great design flexibility and ease of integration. It is fully backward compatible with PCIe 4.0 and 3.1/3.0. A PCIe 5.0 Controller with AXI (formerly XpressRICH-AXI) is also available. The controller […]
An Introduction to HPC computing
https://www.rambus.com/blogs/an-introduction-to-hpc-computing/Written by Steven Woo Dominated by the United States, Japan and China, the high-performance computing (HPC) space is driven by an insatiable demand for ever-higher performance and greater power efficiency. With each new supercomputer debut, the above-mentioned trio sets progressively higher bars with the goal of capturing the highest Top500 score. Summit, Sierra and Sunway […]
Interface IP
https://www.rambus.com/interface-ip/Interface IP Powering accelerated computing with high-performance interface IP Contact Us High-speed interconnects between chips, and between processors and memory, move enormous volumes of data and are key to meeting target performance of advanced computing architectures. Rambus provides state-of-the-art interconnect and memory interface IP consisting of digital controller IP, for PCIe®, CXL®™, HBM, GDDR and […]
Autonomous Vehicles: Memory Requirements & Deep Neural Net Limitations
https://www.rambus.com/blogs/autonomous-vehicles-memory-requirements-deep-neural-net-limitations/Written by Steven Woo Introduction According to the National Highway Traffic Safety Administration (NHTSA), various driver assistance technologies are already helping to save lives and prevent injuries. Specific examples include helping drivers avoid making unsafe lane changes, warning of other vehicles when backing up, or automatically braking when a vehicle ahead stops or slows abruptly. […]
Will Neuromorphic Chips Outpace AI Processors?
https://www.rambus.com/blogs/will-neuromorphic-chips-outpace-ai-processors/Add this one to your list of artificial intelligence (AI) terms — neuromorphic chips. They’re described as chips that model the human brain. That’s what Stanford University professor Kwabena Boahen and other researchers are working on, according to EE Times Rick Merritt’s recent report. The promise coming from these AI researchers is that neuromorphic chips […]
Most Complex Processor Chip for AI Acceleration
https://www.rambus.com/blogs/most-complex-processor-chip-for-ai-acceleration/EE Times reports that Graphcore of Bristol, UK has put on the market a new type of processor for AI acceleration. It’s called the intelligence processing unit (IPU). According to CEO Nigel Toon, the IPU processor, is the most complex processor chip that’s ever been built. It’s described as “just shy of 24 billion transistors on a […]
Training Neural Networks
https://www.rambus.com/blogs/training-neural-networks/by Steven Woo Neural networks (NNs) span a wide range of topologies and sizes. Some neural networks are relatively simple and have only two or three layers of neurons, while so-called deep neural networks may comprise 100+ layers of neurons. In addition, the layers can be extremely wide – with hundreds to thousands of neurons […]
Understanding ML and ANN memory requirements
https://www.rambus.com/blogs/understanding-ml-and-ann-memory-requirements/Written by Steven Woo Artificial Neural Networks First proposed in 1944 by Warren McCullough and Walter Pitts, an artificial neural network (ANN) or more commonly, a neural network (NN), can perhaps best be defined as a computational model that attempts to closely emulate the network of neurons present in the human brain. More specifically, neuromorphic […]
