At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
Found 211 Results
From GDDR to HBM
https://www.rambus.com/blogs/from-gddr-to-hbm-2/A recent KitGuru report suggests AMD has designed its upcoming Radeon R9 380X with high bandwidth memory, or HBM, a next-gen stacked DRAM memory standard. Read first our primer on: HBM2E Implementation & Selection – The Ultimate Guide » “Although HBM provides DDR3 – like bit rate per pin (HBM1=1GHz, HBM2=2GHz), the standard more than […]
On-Chip Noise Monitor
https://www.rambus.com/interface-ip/on-chip-noise-monitor/On-chip Noise Monitor Contact Us Our On-chip Power Supply Noise Monitor is a compact IP block designed to give SoC designers a better understanding of the effects of power supply noise on circuit performance, and ultimately, improve the chip quality and reduce time-to-market. It is embedded directly into the SoC and accurately measuring power supply […]
Northwest Logic Offers MRAM Controller IP compatible with Everspin’s ST-MRAM
https://www.rambus.com/northwest-logic-offers-mram-controller-ip-compatible-everspins-st-mram/Northwest Logic’s MRAM Controller Core is validated with Everspin’s EMD3D064M, expanding the ST-MRAM ecosystem to enable low latency and high reliability storage systems Beaverton, OR – Feb 9, 2015 – Northwest Logic, a leading high-performance IP provider, and Everspin Technologies, Inc., the world’s leading developer and manufacturer of discrete and embedded Magnetic RAM “MRAM”, announces […]
The evolution of LPDDR4
https://www.rambus.com/blogs/the-evolution-of-lpddr4-2/Ajay Jain, a director of product marketing at Rambus, recently told Semiconductor Engineering that LPDDR3 was the “workhorse” of the mobile memory market in 2014. According to Jain, LPDDR3 will retain its heavyweight status throughout most of 2015 before it is supplanted by next-gen LPDDR4. “There are a couple of trends evolving in the mobile […]
Newsroom
https://www.rambus.com/newsroom/Press ReleaseRambus Advances Data Center Server Performance with Industry-First Gen4 DDR5 RCDPress ReleaseRambus Wins 2023 “Most Respected Emerging Public Semiconductor Company” Award from Global Semiconductor AlliancePress ReleaseRambus Protects Data Center Infrastructure with Quantum Safe Engine IPPress ReleaseRambus Boosts AI Performance with 9.6 Gbps HBM3 Memory Controller IP Previous slide Next slide Contact UsGet in touch […]
PHY interoperability highlights industry collaboration
https://www.rambus.com/blogs/phy-interoperability-highlights-industry-collaboration-2/Northwest Logic – a provider of high quality IP cores – is a member of Rambus’ rapidly expanding Partner Program. Recently, the two companies successfully validated interoperability of the Rambus R+™ DDR4/3 PHY with Northwest’s DDR4/3 SDRAM Controller Core. According to senior Rambus exec Frank Ferro, the resulting solution offers customers a differentiated memory subsystem […]
Rambus and Northwest Logic Certify Interoperability of DDR4/3 PHY and Controller
https://www.rambus.com/rambus-northwest-logic-certify-interoperability-ddr43-phy-controller/Integrated IP block achieves both high-performance and efficiency; tested and validated system-level design provides superior signal integrity and reliability SUNNYVALE, Calif. and BEAVERTON, Ore. – August 26, 2014 – Rambus Inc. (NASDAQ:RMBS) and Northwest Logic today announced they have validated interoperability of the Rambus R+™ DDR4/3 PHY with the Northwest Logic DDR4/3 SDRAM Controller Core. […]
Rambus and Northwest Logic Certify Interoperability of DDR4/3 PHY and Controller
https://www.rambus.com/rambus-and-northwest-logic-certify-interoperability-of-ddr43-phy-and-controller/Integrated IP block achieves both high-performance and efficiency; tested and validated system-level design provides superior signal integrity and reliability SUNNYVALE, Calif. and BEAVERTON, Ore. – August 26, 2014 – Rambus Inc. (NASDAQ:RMBS) and Northwest Logic today announced they have validated interoperability of the Rambus R+™ DDR4/3 PHY with the Northwest Logic DDR4/3 SDRAM Controller Core. […]
Northwest Logic’s PCI Express Gen3 Core and S2C’s Virtex-7 ASIC Prototyping Platform fully validated together
https://www.rambus.com/northwest-logics-pci-express-gen3-core-s2cs-virtex-7-asic-prototyping-platform-fully-validated-together/S2C boasts largest Prototype Ready™ interface library in the industry BEAVERTON, Oregon and SAN JOSE, Calif. – August 18, 2014 – Northwest Logic and S2C, Inc. announced today that Northwest Logic’s PCI Express® (PCIe®) 3.0 solution, including the Expresso 3.0 Core (PCI Express 3.0 Controller Core) and family of DMA Cores has been validated on […]
DINI Group Verifies Compatibility of Northwest Logic’s PCI Express Cores with Virtex-7 ASIC Prototyping Platforms
https://www.rambus.com/dini-group-verifies-compatibility-northwest-logics-pci-express-cores-virtex-7-asic-prototyping-platforms/April 29, 2014 – Northwest Logic and DINI Group announced today that Northwest Logic’s PCI Express® (PCIe®) 3.0 solution, including the Expresso 3.0 Core (PCI Express 3.0 Controller Core) has been validated on DINI Group’s 1, 2, and 4-FPGA ASIC prototyping platforms. This validation was done with 4 lanes running at 5 Gbit/s SERDES rates. […]
