PHY interoperability highlights industry collaboration

This entry was posted on Monday, September 15th, 2014.

Northwest Logic – a provider of high quality IP cores – is a member of Rambus’ rapidly expanding Partner Program. Recently, the two companies successfully validated interoperability of the Rambus R+™ DDR4/3 PHY with Northwest’s DDR4/3 SDRAM Controller Core.

According to senior Rambus exec Frank Ferro, the resulting solution offers customers a differentiated memory subsystem that effectively combines optimized signal integrity of the R+ PHY with an advanced controller core.

“R+ DDR4/3 PHY, which maintains full compatibility with industry-standard DDR4 and DDR3 interfaces, delivers versatile configuration options for both area- and power-optimized consumer applications and performance-intensive compute applications,” Ferro told Rambus Press.

“The PHY is currently available in several low-power foundry processes and can be configured for both flip-chip and wire bond packages, with data rates ranging from 800 to 3200Mbps.”

As Ferro explains, Northwest’s DDR4/3 SDRAM Controller Cores are part of a family of silicon-proven, high-performance, easy-to-use memory controller cores that provide support for DDR4/3/2/1 LPDDR4/3/2/1, HBM, MRAM and RLDRAM 3/II. The cores also provide high bus efficiency via request reordering, bank management and look-ahead processing.

“In addition, Northwest Logic offer AXI/AHB bus interface, Error Correction Code (ECC), Read-Modify-Write and Multi-Port Front-End add-on cores to further simplify user designs,” said Ferro. “These cores support the highest memory clock rates, require minimal gate count and, as part of the solution, Northwest Logic offers a complete Memory Test Package for validation.”

It should be noted that Northwest Logic is the latest industry heavyweight to validate product interoperability with Rambus’ DDR4/3 PHY.

Indeed, as we’ve previously discussed on Rambus Press, new silicon starts and IP enablement have become infinitely more complex as well as prohibitively expensive over the years.

“That is why we collaborate closely with our partners, facilitating preferred access to Rambus memory, interfaces and security technology,” added Joe Gullo, Senior Director, Rambus Partner Program. “We continue to combine core competencies in high-speed interface and security solutions with supporting design and validation tools for ASIC designers, foundries, IP developers and EDA companies.”

Interested in learning more? Be sure to check out some of our previous articles on the subject of industry cooperation including “Pairing Rambus R+DDR4/3 PHY with controller IP blocks” and “Shrinking nanometers with Rambus and Globalfoundries.”