At Rambus, we create cutting-edge semiconductor and IP products, providing industry-leading chips and silicon IP to make data faster and safer.
Found 3628 Results
Innovations in CXL 3.0: Novel Device Types, Capabilities, and Interconnects
https://www.rambus.com/innovations-in-cxl-3-0-novel-device-types-capabilities-and-interconnects/CXL 3.0 introduces several compelling new features to address the rapidly evolving demands of future data centers. A new device type, CXL Multi-Headed Devices, has been introduced to support simultaneous connection to multiple hosts. CXL Dynamic Capacity Device (DCD) capability simplifies migration of memory resources between hosts. New CXL Fabrics offer substantial scale and flexibility in architectural design. Danny Moore will discuss these important new developments in the CXL standard.
LPDDR5X: Delivering High Bandwidth and Power Efficiency
https://go.rambus.com/lpddr5x-delivering-high-bandwidth-and-power-efficiency#new_tabThe bandwidth and low power characteristics of LPDDR make it an increasingly attractive choice of memory for applications in IoT, automotive, and edge computing. LPDDR5X takes performance to the next level with a data rate of up to 8.5 Gbps. Join Vinitha Seevaratnam to learn which applications can benefit from using LPDDR memory.
System Level Design Considerations for PCIe 6.0
https://www.rambus.com/system-level-design-considerations-for-pcie-6-0/PCIe 6.0 offers many new and exciting features including a 64 GT/s data rate, PAM4 signaling, forward error correction, and a low power L0p mode. In this presentation, Lou Ternullo will walk you through all the system design considerations you will need to know before getting started on your PCIe 6.0 design, including how to get the most out of each of the PCIe devices.
Leveraging VESA Video Compression & MIPI DSI-2 for High-Performance Displays
https://www.rambus.com/leveraging-vesa-video-compression-mipi-dsi-2-for-high-performance-displays/Visually lossless video compression is essential for handling the growing bandwidth requirements of cutting-edge displays with higher resolutions, faster refresh rates, and greater pixel depths. This presentation will show designers how they can develop cutting-edge display products without compromising on display quality, battery life or cost using a combination of VESA video compression and MIPI DSI-2 technology.
Meeting the Needs of Generative AI Training with HBM3
https://www.rambus.com/meeting-the-needs-of-generative-ai-training-with-hbm3/Generative AI training models are growing in both size and sophistication at a lightning pace, requiring more and more bandwidth. With its unique 2.5D/3D architecture, HBM3 can deliver Terrabytes per second of bandwidth at a system level. Join Frank Ferro to hear how HBM helps designers address the needs of state-of-the-art AI training models.
Powering AI/ML Inference with GDDR6 Memory
https://www.rambus.com/powering-ai-ml-inference-with-gddr6-memory/GDDR6 memory offers an impressive combination of bandwidth, capacity, latency and power. Frank Ferro will discuss how these features make it the ideal memory choice for AI/ML inference at the edge and highlight some of the key design considerations you need to keep in mind when implementing GDDR6 memory at ultra-high data rates.
What’s Next for DDR5 Memory?
https://www.rambus.com/whats-next-for-ddr5-memory/With the industry now firmly on the path to enabling the next generation of servers with DDR5 memory, this presentation will look at what’s next in the DDR5 journey. Hear from John Eble on how DDR5 will scale to advanced performance levels, be deployed in new applications beyond RDIMMs, and how it is tailored for client computing systems.
Emerging Security Challenges in Highly Interconnected Semiconductor Systems
https://www.rambus.com/emerging-security-challenges-in-highly-interconnected-semiconductor-systems/The swift advancements and growing intricacy of highly interconnected semiconductor systems have led to numerous security challenges that pose risks to the integrity, reliability, and performance of modern AI-driven systems. This presentation delves into the primary emerging security threats, such as supply chain attacks, intellectual property theft, hardware Trojans, side-channel attacks, fault injection attacks, and the looming threat of quantum computers. Neeraj Paliwal will examine the consequences of these threats across different industries and discuss how a hardware “secure by design” architectural approach is essential to secure semiconductor systems.
Selecting the right Root of Trust HSM Design for Your Next Project
https://www.rambus.com/selecting-the-right-root-of-trust-hsm-design-for-your-next-project/A Root of Trust is the secure security foundation for a semiconductor or electronic system. In this presentation, Bart Stevens will guide you through the labyrinth of Root of Trust designs, including what problems they can solve and what solutions are available to implement in your next silicon design.
Protecting Devices and Data in the Quantum Era
https://www.rambus.com/protecting-devices-and-data-in-the-quantum-era/Quantum computers will eventually become powerful enough to break traditional asymmetric cryptographic methods, that is, some of the most common security protocols used to protect sensitive electronic data. This presentation will highlight the recent developments in post-quantum cryptography and discuss how designers can get ready for the quantum era.
