At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
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DDR5 Delivers More Bandwidth and Capacity with a Smarter DIMM
https://www.rambus.com/blogs/ddr5-delivers-more-bandwidth-and-capacity-with-a-smarter-dimm/The first wave of DDR5-based servers sport RDIMMs running at 4800 megatransfers per second (MT/s). This is a 50% increase in data rate over top-end 3200 MT/s DDR4 RDIMMs in previous generation high-performance servers. DDR5 memory incorporates a number of innovations, including Decision Feedback Equalization (DFE) and a new DIMM architecture, which enable that speed […]
Rambus Expands Portfolio of DDR5 Memory Interface Chips for Data Centers and PCs
https://www.rambus.com/rambus-expands-portfolio-of-ddr5-memory-interface-chips-for-data-centers-and-pcs/Highlights: Introduces SPD Hub and Temperature Sensor as part of server and client DDR5 memory module chipsets Complements industry-leading DDR5 RCD delivering state-of-the-art bandwidth and capacity Enables enhanced system management and thermal control for improved TCO SAN JOSE, Calif. – July 18, 2022 – Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and […]
Rambus Design Summit Interview Series: Steven Woo
https://www.rambus.com/blogs/rambus-design-summit-interview-series-steven-woo/Rambus Fellow, Steven Woo, returns to the Rambus Design Summit stage tomorrow, and we are so excited for his keynote: Advancing Computing in the Accelerator Age! In our last interview before the show, we met with Steven to chat about his background, CXL, and some of the biggest challenges for computing in the years ahead. Read […]
Rambus Design Summit Interview Series: Ann Keffer
https://www.rambus.com/blogs/rambus-design-summit-interview-series-ann-keffer/We’re so excited that Ann Keffer, Product Marketing Manager at Siemens EDA, will be joining us on the (virtual) stage at Rambus Design Summit! Ahead of the show, we talked to Ann about autonomous driving, what she loves to do in her free time, and growth drivers for the Siemens EDA business. Read on for […]
Testing and debugging PCIe 5.0 devices with INSPECTOR
https://www.rambus.com/testing-and-debugging-pcie5-devices-with-inspector/From concept to production, designing a PCIe 5.0 device requires a long development cycle owed largely to heavy efforts on verification and validation. Today, a large collection of tools enable simulation to find bugs during the verification process or to generate PCIe transactions to validate the device. However, these tools are not enough to provide […]
Rambus Design Summit Interview Series: Justin Endo
https://www.rambus.com/blogs/rambus-design-summit-interview-series-justin-endo/Our partner from Mixel, Justin Endo, is joining us at Rambus Design Summit and we are so excited for his presentation with our own Joe Rodriguez: MIPI® Sensor Solutions for Autonomous Driving. We had the chance to sit down with him before the show to discuss key drivers for MIPI, I3C, and upcoming trends in […]
MACsec-IP-361 Product Brief
https://go.rambus.com/macsec-ip-361-product-brief#new_tabThe MACsec-IP-361 is a plug-and-play solution for adding MACsec on the xMII side of an Ethernet subsystem. It is ideally positioned for designs where the MAC function is tightly integrated with the system-side, for example DMA-MAC Ethernet controllers or switch core IP with integrated MAC modules.
MACsec-IP-361
https://www.rambus.com/security/protocol-engines/macsec-ip-361/MACsec-IP-361 Single-port MACsec Engine with xMII Interface and TSN Support MACsec solution for single-port Ethernet with xMII interface port rates from 1G to 50G, TSN support and ASIL-B ready option Contact Us The MACsec-IP-361 is a plug-and-play solution for adding MACsec on the xMII side of an Ethernet subsystem. It is ISO 26262 ASIL-B Ready […]
PCIe 6.0 Retimer Controller Product Brief
https://go.rambus.com/pcie6-retimer-controller-product-brief#new_tabThe Rambus PCIe 6.0 Retimer Controller provides a highly optimized low-latency data path for signal regeneration. It supports retimer chip PHYs via PIPE 5.2/6.1 interfaces. The control plane interface is provided via CSR (AHB-lite). The PCIe 6.0 Retimer Controller is CXL protocol aware and supports links using 64 GT/s and lower data rates of PCIe.
PCIe 6.0 Retimer Controller with CXL Support
https://www.rambus.com/interface-ip/pci-express/pcie6-retimer-controller/PCIe 6.0 Retimer Controller with CXL Support Contact Us PCI Express® (PCIe®) 6.0 links operating at 64 GT/s using PAM4 signaling have a reach of up to 13 inches at nominal conditions on standard PCBs. Extending trace routing beyond this distance results in higher first bit error rates (FBER) and reduced link efficiency due to […]
