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With high-performance memory experts covering architecture, chips and IP, we’re looking forward to your questions. Please join us for this Ask Me Anything session to get the latest on technology and trends for the world’s highest bandwidth memory solutions including DDR5, HBM3 and GDDR6.
A rapid rise in the size and sophistication of inferencing models has necessitated increasingly powerful hardware deployed at the network edge and in the endpoint devices. To keep these inferencing processors and accelerators fed with data requires a state-of-the-art memory solution that delivers extremely high bandwidth. Frank Ferro will discuss the design and implementation considerations […]
Initially designed for mobile phones and laptops, the bandwidth and low power characteristics of LPDDR make it an increasingly attractive choice of memory for applications in IoT, automotive, edge computing and the data center. Fifth-generation LPDDR5 raises data rates to 6.4 Gbps and bandwidth to 25.6 GB/s for a x32 DRAM device. In this session, […]
The latest generation of the PCI Express, PCIe™ 6.0, advances performance to 64 GT/s in support of advanced workloads and networking. In this presentation, interface technology expert, Arjun Bangre will discuss the changes implemented in PCI Express 6.0, such as PAM4 signaling and low-latency forward error correction (FEC). In addition, Arjun Bangre will contrast PCIe […]
A rapid rise in the size and sophistication of inferencing models has necessitated increasingly powerful hardware deployed at the network edge and in the endpoint devices. To keep these inferencing processors and accelerators fed with data requires a state-of-the-art memory solution that delivers extremely high bandwidth. Frank Ferro will discuss the design and implementation considerations […]
Compute Express Link™ (CXL) has evolved rapidly since its launch in 2019 and is slated for debut in the next generation of server platforms coming later this year. While it builds on the same physical layer as PCI Express, CXL implements unique features at the controller level to enable memory cache coherency between a host […]
With the insatiable need for higher bandwidth in state-of-the-art AI/ML training and HPC, the HBM standard has been on a rapid pace of improvement. The newly standardized HBM3 generation doubles the data rate to 6.4 Gb/s that offers up to 819 GB/s of memory bandwidth between an accelerator and a single HBM3 DRAM device. Memory […]
Moore’s Law has been the force that has shaped the modern world enabling chips with billions of transistors. Yet today, when we need Moore’s Law more than ever, the rate of semiconductor scaling is slowing, requiring system architects to take a new approach to continue the pace of performance gains in computing. Heterogenous compute architectures […]
Modern vehicles incorporate an increasing number of complex integrated circuits. Failures in automotive systems can lead to damage to property, injury or loss of life. Ensuring the reliability of electronic systems is crucial, and the ISO26262 standard documents the requirements for determining automotive functional safety. This whitepaper details the process for how Rambus achieved the […]
The CXL™ Consortium (of which Rambus is a member) has now released the 3.0 specification of the Compute Express Link™ (CXL) standard. CXL 3.0 introduces compelling new features that promise to increase data center performance, scalability and TCO. CXL has evolved rapidly from its introduction in 2019. The 1.0/1.1 specification enabled prototyping of CXL solutions. […]
