At Rambus, we create cutting-edge semiconductor and IP products, providing industry-leading chips and silicon IP to make data faster and safer.
Found 3615 Results
CXL Controller with Zero Latency IDE: You Can’t Do Better Than Zero
https://www.rambus.com/blogs/cxl-controller-with-zero-latency-ide-you-cant-do-better-than-zero/The virtuous cycle of data holds that as volume increases, the value increases. More volume requires faster processing and faster links. More value demands that computing and connecting be secure. That’s why the Compute Express Link™ (CXL) standard specifies that its speedy links be protected by Integrity and Data Encryption (IDE). But if the implementation […]
More capacity and more bandwidth: DDR5 memory enables next-generation data centers
https://go.rambus.com/more-capacity-and-more-bandwidth#new_tabHear Shane Rau, Research Vice President at IDC discuss the market and technology trends surrounding the DDR5 transition, including workloads, hardware needs, market perspectives and industry timing. Joining him, John Eble, Vice President of Product Marketing at Rambus will examine the changes from DDR4 to DDR5 that are enabling more memory capacity and bandwidth critical […]
Rambus and Kioxia Renew Patent License Agreement
https://www.rambus.com/rambus-and-kioxia-renew-patent-license-agreement/SAN JOSE, Calif. – September 21, 2021 – Rambus Inc. (NASDAQ: RMBS), a provider of industry-leading chips and silicon IP making data faster and safer, today announced that it has extended its patent license agreement with Kioxia Corporation, a world leader in memory solutions. Under the terms of the agreement, Rambus patented memory technologies will continue to […]
PCIe 5.0 Controller IP on FPGAs: Current and Future Use Cases
https://www.rambus.com/blogs/pcie5-controller-fpgas/Rambus announced this week that it demonstrated for the first time a PCI Express 5.0 Controller IP (PCIe 5 Controller) operating at 32 GT/s on a leading FPGA platform. “We’ve achieved a new industry benchmark with the demonstration of our PCIe 5.0 Controller operating at 32 GT/s on popular FPGA platforms,” said Scott Houghton, general […]
Rambus True Random Number Generator Certified to NIST SP 800-90B Standard
https://www.rambus.com/blogs/rambus-true-random-number-generator-certified-to-nist-sp-800-90b-standard/Cryptography depends on entropy. More specifically, every cryptographic protocol requires a source of non-deterministic (random) data to seed its security algorithms. While entropy is everywhere and, per the second law of thermodynamics, always increasing, it is exceedingly hard to create an unpredictable, statistically independent, uniformly distributed and protected source of data. In other words, creating a true random number generator is quite […]
Rambus Demonstrates Industry-first PCIe® 5.0 Digital Controller IP for FPGAs
https://www.rambus.com/rambus-demonstrates-industry-first-pcie5-digital-controller-ip-for-fpgas/Highlights: Achieves industry-first demonstration of 32 GT/s PCIe 5.0 Digital Controller IP operation on leading FPGA platforms Expands use models for FPGAs by enabling multi-instance, PCIe 5.0 switching and bridging at 32 GT/s speeds Enhances performance and capabilities of FPGAs for use in emulation and prototyping, test and measurement, aerospace and defense, and storage and […]
Rambus Design Summit Featured Speaker: Steven Woo
https://www.rambus.com/blogs/rambus-design-summit-featured-speaker-steven-woo/Another week, another Rambus Design Summit wrap up! Over the coming weeks, we will be featuring sessions from RDS 2021 with key takeaways and speaker highlights. This week we are featuring… Session Topic: Emerging Compute Architectures for the Evolving Data Center Rambus fellow and distinguished inventor, Dr. Steven Woo, kicked off the Rambus Design Summit […]
CXL 2.0 Controller Product Brief
https://go.rambus.com/cxl2-controller-product-brief#new_tabThe Rambus Compute Express Link (CXL) 2.0 Controller leverages a silicon-proven PCIe 5.0 controller architecture for the CXL.io path, and adds CXL.cache and CXL.mem paths specific to the CXL standard.
CXL 2.0 Controller with AXI Product Brief
https://go.rambus.com/cxl2-controller-axi-product-brief#new_tabThe Rambus Compute Express Link (CXL) 2.0 Controller with AXI leverages a silicon-proven PCIe 5.0 controller architecture for the CXL.io path, and adds CXL.cache and CXL.mem paths specific to the CXL standard. This controller offers support of the AMBA AXI, CPI and AMBA CXS-B protocol specifications.
PCIe 5.0 Controller with AXI Product Brief
https://go.rambus.com/pcie5-controller-axi-product-brief#new_tabThe Rambus PCIe 5.0 controller with AXI is designed for maximum performance and ease of use for PCI Express (PCIe) 5.0 applications. It comprises a complete SerDes subsystem with the Rambus PCIe 5.0 PHY or can integrate with PIPE 5.x-compliant 3rd-party PHYs. The controller is backwards compatible with PCIe 4.0, and 3.1/3.0.
