At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
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Rambus Licenses DPA Countermeasures to Utimaco
https://www.rambus.com/rambus-licenses-dpa-countermeasures-to-utimaco/Cutting-edge hardware-based security technologies protect against side-channel attacks SUNNYVALE, Calif. – March 25, 2020 – Rambus Inc. (NASDAQ: RMBS) a premier silicon IP and chip provider making data faster and safer, today announced that it has signed a patent license agreement with Utimaco, a leading supplier of Hardware Security Modules (HSMs). The agreement includes the […]
In-Line ECC Product Brief
https://go.rambus.com/in-line-ecc-core-product-brief#new_tabPart of a full suite of memory controller add-on cores, the In-Line Error Correction Coding (In-Line ECC) core works with the Northwest Logic GDDR6 and LPDDR4 Controller cores. The In-Line ECC implements the standard Hamming Code-based DRAM Single Error Correction (SEC) and Double Error Detection (DED) algorithm.
2.5D/3D Packaging Solutions for AI and HPC (Chinese)
https://go.rambus.com/packaging-solutions-for-ai-and-hpc-chinese#new_tabFor AI and HPC applications, HBM2E memory can deliver excellent bandwidth, capacity and latency in a very compact footprint thanks to its 2.5D/3D structure. The flipside is that this same structure leads to greater design complexity and raises a new set of implementation considerations.
Memory Systems for AI: Part 5
https://www.rambus.com/blogs/memory-systems-for-ai-part-5/Written by Steven Woo for Rambus Press In part four of this series, we took a closer look at the Roofline model, a modern computer architecture tool that illustrates how applications like artificial intelligence (AI) programs perform on different processor architectures like Google’s tensor processing unit (TPU), NVIDIA’s K80 GPU and Intel’s Haswell CPU. In […]
Securing the Silicon Supply Chain
https://medium.com/supplyframe-hardware/securing-the-silicon-supply-chain-2499474d6387#new_tabI don’t know about you, but when I hear the name Rambus, I think of the company that was founded in 1990. I remember them leaping into the limelight with a fanfare of trumpets. Well, if the truth be told, it was with their 600 MHz interface technology, which addressed the memory bottleneck issues being […]
5G and AI Raise Security Risks for IoT Devices
https://go.rambus.com/5g-and-ai-raise-security-risks-for-iot-devices-webinar#new_tab5G represents a revolution in mobile technology with performance that will rival that of wireline networks. 5G’s Ultra-reliable Low Latency Communication (uRLLC) links will enable a profusion of artificial intelligence (AI)-powered IoT devices from delivery drones to smart cities. The rapid rise in the number of smart IoT devices, coupled with expanded connectivity, will greatly […]
Dangers of Counterfeit Semi Chips
https://www.designnews.com/cyber-security/dangers-counterfeit-semi-chips/122302744362434#new_tabIn 2019, the worldwide fake semi market was estimated at $75 billion according to Industry Week. This counterfeit chip market particularly prevalent in the government and defense industries. According to a US government report, more than 1 million counterfeit electronic components were used in 1,800 instances affecting military aircraft and missiles.
Memory Systems for AI: Part 4
https://www.rambus.com/blogs/memory-systems-for-ai-part-4/Written by Steven Woo for Rambus Press In part three of this series, we discussed how a Roofline model can help system designers better understand if the performance of applications running on specific processors is limited more by compute resources, or by memory bandwidth. Rooflines are particularly useful when analyzing machine learning applications like neural […]
Rambus’ HBM2E Memory Controller & PHY Offer Chipmakers Cost-Effective Designs
https://www.tomshardware.com/news/rambus-hbm2e-memory-controller-phy-designs#new_tabThe latest generation of high-bandwidth memory, HBM2E, is around the corner. Now that Samsung has started mass production of its HBM2E memory stacks, Rambus has unveiled its controller and PHY (physical interface) designs.
Rambus Develops HBM2E Controller & PHY: 3.2 Gbps, 1024-Bit Bus
https://www.anandtech.com/show/15599/rambus-develops-hbm2e-controller-phy-32-gbps-1024bit-bus#new_tabThe latest enhancements to the HBM2 standard will clearly be appreciated by developers of memory bandwidth-hungry ASICs, however in order to add support of HBM2E to their designs, they are also going to need an appropriate controller as well as physical interface. For many companies developing of such IP in-house does not make financial sense, so […]
