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Rambus’ Suresh Andani has written a detailed Semiconductor Engineering article that explores how PCIe 5 can effectively accelerate AI and ML applications. According to Andani, the rapid adoption of sophisticated artificial intelligence/machine learning (AI/ML) applications and the shift to cloud-based workloads has significantly increased network traffic in recent years. However, the paradigm of virtualization can […]
John Shinn Senior Vice President & General Counsel John Shinn is Rambus’ Senior Vice President and General Counsel. John joined Rambus in October 2016 and assumed the role of General Counsel in 2021. Prior to Rambus, John held senior legal executive roles at both private and public companies in the Silicon Valley, where he was […]
Rambus’ Tim Messegee has penned an article for Semiconductor Engineering that takes an in-depth look at the importance of ensuring security at the intersection of AI and 5G. As Messegee notes, 5G represents nothing less than a revolution in mobile technology with performance that is poised to rival that of wireline networks. “Relative to its […]
Delivered strong Q4 results, in line with revenue and exceeding profitability expectations Beat 2020 guidance for annual revenue and earnings Generated $185.5 million in cash provided by operating activities for the full year, up 44% year over year Record annual product revenue of $114.0 million driven by Memory Interface Chips, up 56% year over year […]
Building security in an SoC aiming to meet the goals set by the ARM Platform Security Architecture (PSA) is a complex matter. This is compounded by the complexity of modern-day SoCs comprising multiple processors, security domains and security levels. The Rambus root of trust provides a solid foundation for the SoC security architecture ticking ‘all […]
HiPEAC, a European network of almost 2,000 world-class computing systems researchers, named Matthias Jung (Fraunhofer IESE), Lukas Steiner, and Norbert Wehn (TUK) as winners of the prestigious Tech Transfer Award for their work on DRAMSys4.0. With an ongoing collaboration with Fraunhofer IESE on DRAMSys4.0, Rambus salutes the award recipients. “The work Fraunhofer IESE had done […]
Designed to be integrated in power and space-constrained SoCs or FPGAs, the RT-260 Root of Trust (formerly VaultIP) is a FIPS 140-2 compliant hardware core that guards the most sensitive assets on chips and establishes the foundation for platform security.
Designed to be integrated in power and space-constrained SoCs or FPGAs, the RT-131 Root of Trust (formerly VaultIP) is a FIPS 140-2 compliant hardware core that guards the most sensitive assets on chips and establishes the foundation for platform security.
Designed to be integrated in power and space-constrained SoCs or FPGAs, the RT-130 Root of Trust (formerly VaultIP) is a FIPS 140-2 compliant hardware core that guards the most sensitive assets on chips and establishes the foundation for platform security.
Designed to be integrated in power and space-constrained SoCs or FPGAs, the RT-121 Root of Trust (formerly VaultIP) is a FIPS 140-2 compliant hardware core that guards the most sensitive assets on chips and establishes the foundation for platform security.
