At Rambus, we create cutting-edge semiconductor and IP products, providing industry-leading chips and silicon IP to make data faster and safer.
Found 3616 Results
Rambus IPsec Packet Engine Secures 5G Networking at 10 Gbps
https://www.rambus.com/rambus-ipsec-packet-engine-secures-5g-networking-at-10-gbps/Highlights: Internet Protocol Security (IPsec) Packet Engine with integrated Data Plane Development Kit (DPDK) and companion key negotiation toolkit provides complete solution for securing 5G networking from 1 to 10 Gbps data rates Easily integrates into SoCs for 5G base stations, core network, gateways and end points Supports 3GPP, TLS, DTLS protocols, all relevant IPsec […]
4Gbps！HBM2E内存接口再现性能标杆
https://www.eet-china.com/news/10020.html#new_tab人工智能/机器学习(AI/ML)在全球范围内的迅速兴起，正推动着制造业、交通、医疗、教育和金融等各个领域的惊人发展。从2012年到2019年，人工智能训练能力增长了30万倍，平均每3.43个月翻一番，就是最有力的证明。支持这一发展速度需要的远不止摩尔定律，人工智能计算机硬件和软件的各个方面都需要不断的快速改进。
Impact of AI on Data Center Infrastructure
https://www.delloro.com/impact-of-ai-on-data-center-infrastructure/#new_tabThe 3rd AI Hardware Summit took place virtually earlier this month and it was exciting to see how quickly the ecosystem has evolved and to learn of the challenges the industry has to solve in scaling artificial intelligence (AI) infrastructure. I would like to share highlights of the Summit, along with other notable observations from the industry […]
Rambus Design Summit 2020
https://www.rambus.com/blogs/rambus-design-summit-2020/On October 8th, technology experts from across Rambus came together for a virtual summit to present on the selection and implementation of IP solutions for the data center, 5G/edge and IoT devices. In addition, Ed Sperling of Semiconductor Engineering and Shane Rau of IDC joined Rambus executives Neeraj Paliwal, Matt Jones and John Eble for […]
How Bandwidth is Key to Unlocking Greater AI Performance
https://www.rambus.com/how-bandwidth-is-key-to-unlocking-greater-ai-performance/Rambus fellow and distinguished inventor, Dr. Steven Woo, explores the latest developments in AI/ML training and inference. AI/ML performance is advancing at an astonishing rate thanks to purpose-built AI accelerators. Dr. Woo discusses how emerging memory and system interfaces are key to providing the bandwidth needed for the next generation of AI/ML hardware.
Security for Design Approach for Semiconductors
https://www.rambus.com/security-for-design-approach-for-semiconductors/Facing a growing matrix of threats, semiconductors must be designed with security as a fundamental consideration. In this webinar, Rambus VP and General Manager for Rambus Security, Neeraj Paliwal, discusses the principles and methodologies for secure chip design and provisioning.
Data Center Evolution
https://www.rambus.com/data-center-evolution/Ed Sperling, Editor in Chief of Semiconductor Engineering moderates a far-ranging roundtable on the future of data center development. IDC research vice president, Shane Rau, discusses the macro trends and their impact on compute and network device architectures. Technology leaders from across Rambus will share the chip and IP solutions that can take data center performance and security to the next level.
Choosing the Right Root of Trust
https://www.rambus.com/choosing-the-right-root-of-trust/A hardware root of trust (RoT) provides the secure foundation for a chip or electronic system. A broad range of RoT solutions are available for implementation. In this webinar, Rambus security expert, Bart Stevens, will discuss the considerations for selecting the right root of trust for a target application.
Protecting Data in Motion with MACsec
https://www.rambus.com/protecting-data-in-motion-with-macsec/Providing Layer 2 security, MACsec is becoming the predominant solution for safeguarding network traffic. In this webinar, Rambus security expert, Gijs Willemse, will discuss the design and implementation of hardware-based MACsec security. The Rambus MACsec protocol engines with performance to 800G will be covered.
PCI Express Selection and Implementation
https://www.rambus.com/pci-express-selection-and-implementation/The latest generation of the PCI Express, PCIe 5.0, advances performance to 32 GT/s in support of advanced applications including 400G Ethernet. In this webinar, Rambus technology experts Phani Paladugu and Vinitha Seevaratnam discuss the selection and implementation considerations for PCI Express solutions. The silicon-proven Rambus PCIe 5.0 interface solution consisting of integrated PHY and memory controller is covered.
