At Rambus, we create cutting-edge semiconductor and IP products, providing industry-leading chips and silicon IP to make data faster and safer.
Found 3635 Results
Read-Modify-Write Core Product Brief
https://go.rambus.com/read-modify-write-core-product-brief#new_tabPart of a full suite of memory controller add-on cores, the Read-Modify-Write Core handles misaligned bursts when an Error Correction Code (ECC) is being used. Read-Modify-Write write operations are by their very nature inefficient. The Read-Modify-Write core implements a prefetch architecture that maximizes the memory bus utilization as efficiently as possible.
Memory Test Analyzer Core Product Brief
https://go.rambus.com/memory-test-analyzer-core-product-brief#new_tabPart of a full suite of memory controller add-on cores, the Memory Test Analyzer Core can be used in conjunction with the Memory Test Core to capture actual and expected test data. The core is useful for chip and board validation. It provides low-cost, built-in logic analyzer capability similar in concept to FPGA-based internal logic […]
Multi-Port Front-End Core Product Brief
https://go.rambus.com/multi-port-front-end-core-product-brief#new_tabPart of a full suite of memory controller add-on cores, the Multi-Port Front-End Core provides a multi-port interface to Northwest Logic memory controller cores.
AXI Interface Core Product Brief
https://go.rambus.com/axi-interface-core-product-brief#new_tabPart of a full suite of memory controller add-on cores, the AXI Interface Core is designed for use in applications requiring ARM’s Advanced eXtensible Interface (AXI). It requires the Read-Modify-Write core which is available separately.
Memory Test Core Product Brief
https://go.rambus.com/memory-test-core-product-brief#new_tabPart of a full suite of memory controller add-on cores, the Memory Test Core provides comprehensive memory test support for chip and board verification. It can be used in conjunction with the Mem Test Analyzer Core to capture the actual and expected test data.
Reorder Core Product Brief
https://go.rambus.com/reorder-core-product-brief#new_tabPart of a full suite of memory controller add-on cores, the Reorder Core reorders requests based first on priority and second on throughput optimization. Throughput optimization includes moving same bank/same row requests next to each other, same bank/different row requests away from each other, moving reads next to reads and writes next to writes.
ECC Core Product Brief
https://go.rambus.com/ecc-core-product-brief#new_tabPart of a full suite of memory controller add-on cores, the Error Correction Coding (ECC) core implements the standard Hamming Code-based DRAM Single Error Correction (SEC) and Double Error Detection (DED) algorithms. The Read-Modify-Write core, offered separately, can be used in conjunction with the ECC Core when dealing with misaligned bursts.
PCIe 4.0 Controller Product Brief
https://go.rambus.com/pcie4-controller-product-brief#new_tabThe PLDA PCIe 4.0 Controller is designed to achieve maximum PCI Express (PCIe) 4.0 performance with great design flexibility and ease of integration. It comprises a complete SerDes subsystems with the Rambus PCIe 4.0 PHY or can integrate with PIPE 4.2-compliant 3rd-party PHYs. The controller is backwards compatible with PCIe 3.1/3.0.
MIPI Testbench Product Brief
https://go.rambus.com/mipi-testbench-product-brief#new_tabThe Northwest Logic MIPI Testbench emulates a MIPI device enabling end-to-end simulation of a MIPI design. It includes separate versions for CSI-2 Transmit, CSI-2 Receive, DSI-2 Host (Transmit), DSI-2 Peripheral (Receive), DSI Host, and DSI Peripheral.
CSI-2 Controller Product Brief
https://go.rambus.com/csi-2-controller-product-brief#new_tabThe Northwest Logic CSI-2 controller core is a second-generation MIPI CSI-2 core optimized for high performance, low power and small size. The core is fully compliant with the CSI-2 standard and implements all three layers defined therein: Pixel to Byte Packing, Low Level Protocol, and Lane Management.
