Highlights:
- GDDR6, HBM2, and 112G Long Reach (LR) interfaces designed for TSMC’s industry-leading N7 process technology expand Rambus’ leading-edge memory and SerDes PHY offerings
- Portfolio enables critical building blocks for next-generation data center, networking, wireless 5G, high-performance computing (HPC), advanced driver assistance systems (ADAS), artificial intelligence (AI) and machine learning (ML) applications
SUNNYVALE, Calif. and SANTA CLARA, Calif. – Sep. 23, 2019 – Rambus Inc. (NASDAQ: RMBS), a premier silicon IP and chip provider making data faster and safer, today announced a broad portfolio of high-speed memory and SerDes PHYs for next-generation applications on TSMC’s industry-leading N7 process technology. Leveraging almost 30 years of high-speed interface design expertise and using leading process technology, Rambus offers GDDR6, HBM2 and 112G LR PHY IP available for licensing. These solutions enable demanding applications for data center, networking, wireless 5G, HPC, ADAS, AI and ML.
As the fastest discrete memory interface from Rambus, GDDR6 memory PHY adds to TSMC’s most comprehensive portfolio of silicon-proven intellectual property (IP), design tools and Reference Flows through the TSMC IP Alliance Program, a key component of TSMC Open Innovation Platform® (OIP). Along with HBM2 and 112G LR SerDes PHY, Rambus offers leading-edge memory and serial link interfaces for a broad range of high-performance applications.
“TSMC OIP Alliance partners continue to deliver innovative solutions that will address the tremendous demands for computing power driven by AI and next-generation networks,” said Suk Lee, TSMC senior director, Design Infrastructure Management Division. “We’re pleased with the availability of Rambus’ high-speed memory and SerDes interface solutions on TSMC’s industry-leading N7 process technology to address customer’s requirements for the most demanding applications.”
Expanding beyond the traditional GPU and graphics applications, GDDR6 and HBM2 address market needs in multiple, advanced applications like AI/ML, ADAS and networking, as memory bandwidth becomes more critical for overall system performance. As the industry rapidly transitions to 400 and 800GbE communications systems, 112G LR is a key building block necessary to support the ever-growing demand for more bandwidth in data center and network applications.
“This announcement highlights Rambus’ leadership in high-speed SerDes and memory PHY IP, leveraging the company’s long tradition of signal- and power-integrity expertise,” said Hemant Dhulla, vice president and general manager of IP cores at Rambus. “We are very proud to be able to offer these advanced solutions as part of the TSMC ecosystem.”
Availability
The Rambus GDDR6 and HBM2 Memory PHYs, and 112G LR SerDes PHY are available from Rambus today for licensing and integrating into system-on-chip (SoC) designs.
Demonstration Details at TSMC 2019 Open Innovation Platform® Ecosystem Forum
Join Rambus in Booth #408 at the TSMC 2019 Open Innovation Platform® Ecosystem Forum on September 26, 2019 at the Santa Clara Convention Center in Santa Clara, California and learn more about its extensive portfolio of interface IP and innovation in advanced memory and interface technology.
Additional Information
To learn more about the TSMC 2019 Open Innovation Platform® Ecosystem Forum, visit https://www.rambus.com/event/tsmc-oip-santa-clara-2019/. For additional details about Rambus silicon applications or more information on our latest Rambus high-speed memory and SerDes PHY solutions, go to rambus.com/interface-ip/.
