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3DES-IP-16

3DES-IP-16 3DES ECB/CBC Accelerators

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The 3DES-IP-16 (EIP-16) is IP for accelerating the AES symmetric cipher algorithm (FIPS-46/81 – SP800-IP-20), supporting single Des and triple DES in ECB, CBC, CFB and OFB modes up to 4 Gbps @ 800MHz. Designed for fast integration, low gate count and full transforms, the 3DES-IP-16 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into high speed crypto pipelines.

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3DES family of accelerators.

Available in three configurations / performance grades.

Library element for security packet engines.

How the 3DES-IP-16 3DES ECB/CBC Accelerators work

The 3DES-IP-16 is a family of the cryptographic library elements in the Rambus hardware IP library (formerly of Inside Secure). For example, the 3DES-IP-16 is the cipher core embedded in all IPsec protocol aware security engines. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.

Sustained performance for any object sizes ranges up to 4 Gbps depending on the configuration and area. Gate count is between 9K and 15K gates depending on the configuration. Multiple 3DES-IP-16 cores can be cascaded.

Rambus also offers the AES-IP-39 that supports AES modes and can be provided with countermeasures including ones against side-channel attacks and fault injection attacks.

3DES-IP-16 3DES ECB/CBC Accelerator Information

Key benefits:

Silicon-proven implementation
Fast and easy to integrate into SoCs
Flexible layered design
Complete range of configurations
World-class technical support

Features:

Wide bus interface (64-bit data, 192-bit keys, 64-bit IV) or 32 bit register interface.
Key sizes: 64 and 192 bits.
Feedback modes: ECB, CBC, OFB (1, 8 and 128 bit),  CFB (1, 8 and 128 bit).
Low Speed, Medium Speed, High Speed versions.
Fully synchronous design.

Alternatives:

AES-IP-32 AES ECB accelerators
AES-IP-36 AES ECB/CBC/CTR accelerators
AES-IP-37 AES Key Wrap accelerators
AES-IP-38 AES XTS/GCM accelerators
AES-IP-39 AES ECB/CBC/CTR/CCM/GCM accelerators

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Related Markets & Applications

CRYPT-IP-120

CRYPT-IP-120 AES Crypto, SHA-2 Hash Core with DMA

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The CRYPT-IP-120 combines local key storage, an AES cipher (AES-IP-39), a SHA-2 hash (HASH-IP-57) and DMA capability into an easy to integrate, silicon-proven package. Designed for fast integration into SoCs, and featuring low gate count and full transforms, the CRYPT-IP-120 DMA crypto engine provides a reliable and cost-effective embedded solution for high speed processing pipelines.

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AES, SHA-2, and DMA in a single IP core

Performance @ 500MHz

1 Gbps AES-128, 192
8 Gbps AES-256
4 Gbps SHA-256

Optional algorithms and customization

CRYPT-120 Advantages

The CRYPT-IP-120 DMA crypto core provides hardware cryptographic algorithm implementations for optimal performance, user experience, battery lifetime and robust security.

Significant performance boost compared to software execution on the host processor.
Ability to store keys in an integrated RAM via DMA, and keep these inaccessible from (but usable by) the host/application.

The flexibility of the CRYPT-IP-120 architecture allows customization to individual requirements, including SNOW3G, Kasumi, AES-XTS and other basic IP modules.

CRYPT-IP-120 Features

Specifications	CRYPT-IP-120b	CRYPT-IP-120c-c	CRYPT-IP-120c-h	CRYPT-IP-120d-h	CRYPT-IP-120f
Control Interface	Simple register based control interface Operation done interrupt DMA done interrupt
DMA Controller⁴
AHB Master & Slave Interfaces⁵
Local Key Store³
AES¹
SHA		224, 256	224, 256, 384, 512²	224, 256, 384, 512²	224, 256
Gate Count (fab and process node-dependent)	49-53K

Notes:

AES Algorithm (AES)

- 128, 192 and 256-bit key support
- AES-ECB/CBC/CTR
- AES-CBC-MAC
- AES-CCM
- AES-GCM (Optional, by default available)
- Internal GCM hash key calculation
- Key load via the Key Store only
- IV writing and reading via slave interface
- Data load via the slave and DMA
- Data readout via the slave and DMA
- Tag readout via the slave and DMA

Hash Configuration

- Basic hash
- HMAC (using several basic hash operations)
- Digest and length load via the slave
- Data load via the slave and DMA
- Digest readout via the slave and DMA

Key Store

- Secure management of sensitive security parameters
- Local 8 x 128-bit (or 4 x 192-bit/256-bit) encryption key storage
- Writable via DMA only
- Key store RAM: 32×32 bit 1 port RAM

DMA controller

- Two channels (inbound, outbound)
- 16-bit DMA length

AMBA interface

- AHB interface (AMBA V2.0)
  - 32-bit AHB slave interface for configuration and data
  - 32-bit AHB master interface for keys, crypto and hash blocks
  - Optional use of privileged accesses for key reads
- AXI interface (AMBA V3.0)
  - 32-bit and 64-bit AXI master and slave interface available on request