Memory PHYs
Introducing the Rambus GDDR6 Memory PHY
The Rambus GDDR6 Memory PHY IP Core Rambus has officially announced its GDDR6 (Graphics Double Data Rate) Memory PHY IP Core. According to Luc Seraphin,
March 11, 2019
At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
Memory PHYs
Let’s talk about 7nm
Frank Ferro, a senior director of product management at Rambus, recently penned an article for Semiconductor Engineering about the promises and challenges of 7 nanometers
March 11, 2019
Memory PHYs
Pre-verified chiplets gain traction as NRE costs rise
Pre-verified chiplets Ann Steffora Mutschler of Semiconductor Engineering recently penned an article that explores how the concept of building silicon from pre-verified chiplets is beginning
March 11, 2019
Memory PHYs
Rambus validates interoperability of DDR4 high-performance memory IP solution for Arm-based data center systems
Rambus’ DDR4 PHY and Arm’s CoreLink DMC-620 Dynamic Memory Controller Today, we announced the validated interoperability of Rambus’ DDR4 PHY and Arm’s CoreLink DMC-620 Dynamic
March 11, 2019
Memory PHYs
Living on the edge with 5G and fog computing
From 4G to 5G The current 4G cellular networks that drive our computers, tablets and smartphones are poised for a major upgrade as we approach
March 11, 2019
Memory PHYs
Rambus highlights HBM2 PHY collaboration at GLOBALFOUNDRIES Technology Conference
HBM2 PHY We are showcasing our HBM2 PHY at the GLOBALFOUNDRIES Technology Conference at the Hyatt Regency Santa Clara (table #6). Designed for systems that
December 29, 2020
