Building a robust HBM2 PHY
This entry was posted on Thursday, February 16th, 2017.
What is HBM?
HBM is a high-performance memory that features reduced power consumption and a small form factor. More specifically, it combines 2.5D packaging with a wider interface at a lower clock speed (as compared to DDR4) to deliver higher overall throughput at a higher bandwidth-per-watt efficiency for high-performance computing applications.
Originally targeted at the graphics industry, HBM continues to gain momentum in the server and networking markets as system designers work to move higher bandwidth closer to the CPU. Expanding DRAM capacity – which boosts overall system performance – allows data centers to maximize local DRAM storage for wide throughput. Indeed, HBM DRAM architecture effectively increases system memory bandwidth by providing a wide interface to the SoC of 1024 bits. The maximum speed of HBM2 is 2Gbits/s, or a total bandwidth of 256Gbytes/s. Although the bit rate is similar to DDR3 at 2.1Gbps, the eight 128-bit channels provide HBM with approximately 15x more bandwidth.
HBM modules are connected to the SoC via a silicon or organic interposer. A short and controlled channel between the memory and the SoC requires less drive from the memory interface, thus reducing the power when compared to DIMM interfaces. In addition, since the interface is wide, system designers can achieve very high bandwidth with a slower frequency.
The challenges of building a robust HBM2 PHY
According to Frank Ferro, a senior director of product management at Rambus, there are multiple challenges associated with the design of robust HBM2 PHYs.
“One such challenge is maintaining signal integrity at speeds of two gigabits per pin throughout via the interposer. This is why extensive modeling of both signal and power integrity is essential to achieving reliable operation in the field,” he explained in a recent in Semiconductor Engineering article. “As such, HBM PHY design engineers should possess extensive knowledge of 2.5D design techniques, along with a comprehensive understanding of system behavior under various conditions including temperature and voltage variations.”
In addition, determining signal routing tradeoffs via the interposer presents engineers with another significant challenge. These tradeoffs, says Ferro, entail balancing the ability to maintain optimal system performance while keeping the cost of the interposer as low as possible. For example, design teams must decide if one or two signal routing layers should be used throughout the interposer.
“Although one routing layer saves cost, it demands a more challenging design with narrower channel widths and higher crosstalk,” he continued. “Moreover, design teams need to determine how far apart the ASIC can be moved from the HBM DRAM modules on the interposer. While farther distances can help with thermal dissipation, each millimeter increases the likelihood of signal integrity issues.”
The implementation of 2.5D technology in HBM2 systems adds numerous manufacturing complexities, requiring PHY vendors to work closely with multiple entities, such as semiconductor, manufacturing partner (foundry) and packaging house. As Ferro emphasizes, careful design of the entire system – including SoC, interposer, DRAM and package – are essential to ensure high yield and proper system operation. In addition, having a high yielding module is a critical element of keeping costs in check, given the number of expensive components, including the SoC, multiple HBM die stacks and interposer.
“Even with these challenges, the advantages of having increased memory bandwidth and density closer to the CPU clearly improves overall system efficiency for server and networking systems,” Ferro added.
The Rambus High Bandwidth Memory (HBM) Gen2 PHY
It should be noted that Rambus recently announced the availability of its new High Bandwidth Memory (HBM) Gen2 PHY. Designed for systems that require low latency and high bandwidth memory, our HBM PHY is built on the GLOBALFOUNDRIES advanced 14nm Power Plus (LPP) process technology. The PHY – which is fully compliant with the JEDEC HBM2 standard – supports data rates up to 2000 Mbps per data pin, resulting in a total bandwidth of 256 GB/s. The interface features 8 independent channels, each containing 128 bits for a total data width of 1024 bits, as well as support for a stack height of 2, 4 or 8 DRAMs.
The PHY is designed for a 2.5D system with an interposer for routing signals between the DRAM and PHY. The combination of signal density and stacked form factor requires special design consideration. To enable easy implementation and improved flexibility of design, we perform complete signal and power integrity analysis on the entire 2.5D system to ensure that all signal, power and thermal requirements are met. The HBM Gen2 PHY – delivered as a fully characterized hard macro – includes all necessary components for robust operation, such as IO pads, PLL, clock distribution, transmit and receive paths, control logic, power distribution and electrostatic discharge (ESD) protection circuitry.
Key Rambus HBM Gen2 PHY product highlights include support for DRAM 2, 4 and 8 stack height, a DFI-style interface to the memory controller, 2.5D interposer connections between the PHY and DRAM, a validated memory controller interface, support for wafer-level and interposer testing, as well as availability with LabStation™ Validation Platform for enhanced bring-up and validation.
Additional features include a flexible delivery of the IP core (works with ASIC/ SoC layout requirements), 8 channels and 16 pseudo-channels, selectable low-power operating states, programmable output impedance, pin programmable support for lane repair, ZQ calibration of output impedance, IEEE 1500 test support, SSO noise reduction, micro-bump pitch matched to the DRAM pitch, east-west orientation (PHY can be placed in corner of die) and a register interface for state observation.