Semiconductor Engineering Editor in Chief Ed Sperling recently noted that getting data in and out of memory is just as important as optimizing the speed and efficiency of a processor.
“[Nevertheless], for years design teams managed to skirt the issue because it was quicker, easier and less expensive to boost processor clock frequencies with a brute-force approach,” he explained. “That worked well enough prior to 90nm, and adding more cores at lower clock speeds filled the gap starting at 65nm.”
According to Sperling, the subsequent solution of choice amounted to packing more SRAM around processors. To be sure, some SoCs are now up to 80% memory, which is not considered the most efficient way to design chips.
For one thing, says Sperling, it puts the onus on operating system, middleware and embedded software teams to integrate the flow of data and make it all work. Indeed, even though this approach has been well tested and market-proven, it too is beginning to run out of steam.
“That puts chipmakers back in front of the original challenge of getting data in and out of memory more efficiently, but with some new hurdles and options,” he confirmed.
Such hurdles include interconnects, wires, thinning gate oxides and an increasing number of cores. Fortunately, the commercialization of fan-outs and 2.5D approaches has allowed chipmakers to rethink how and where to add memory on the Z-axis. Concurrently, new memory types are offering new options to balance cost, performance and data reliability.
As Rambus VP of solutions marketing Steven Woo puts it, there are a number of possible scenarios that could influence the architecture and integration of various IP blocks to evolve a new memory paradigm.
“You could make processors with lots and lots of cache, or you can use smaller die, more processors, and higher-bandwidth memory,” he explained. “For the low power community, you want to look at where power is being wasted. Moving data long distances is wasteful, which is why in phones you see the memories located very close to the processor.”
With something like Wide I/O, says Woo, a system would use a lot of wires at lower speed, rather than a few wires at high speed.
“You get better performance characteristics that way. What we’re witnessing is that the physical design envelope is changing. It’s no longer design in isolation. Packaging is changing, and that’s changing other things,” he continued. “TSVs are a change to the value chain and the way DRAMs are sold. When they’re assembled, there are a host of other issues, like where it can go bad and whether it went bad in assembly. Packaging changes the relationships between the players, too.”
In addition, says Woo, there are established methods for determining where things went wrong, but those signals might now inaccessible. He describes it as a big equation: “When the benefits outweigh the cost of assembly, test and manufacturing, then people adopt it.”
Woo also confirmed that the industry has seen a move to near-data processing – with data sets so large that it has become cheaper to move the processor closer to the data, rather than shift the data closer to the processor.
“There’s also a movement to minimize the data through semantic awareness, where you understand the structure of the data and you walk down a list of what’s done right in memory and an FPGA instead of having to return to a Xeon processor,” he added.
As Sperling points out, one concept has become crystal clear despite a still-evolving model.
“Memory is no longer just a checklist item in any advanced designs. It’s now an integral part of the design, and it can be tweaked, bent and twisted in ways that were largely ignored in the past to improve performance, reduce power, and create differentiation,” he concluded.
Interested in learning more? The full text of “Rethinking Memory” by Ed Sperling is available on Semiconductor Engineering here.