Next-gen server DIMM buffer chipset targets DDR5 memory

This entry was posted on Wednesday, September 20th, 2017.

Rambus has announced functional silicon of a double data rate (DDR) server DIMM (dual inline memory module) buffer chipset prototype targeted for next-gen DDR5 memory technology.

According to Luc Seraphin, senior vice president and general manager of the Rambus Memory and Interfaces Division, the announcement marks a key milestone for both Rambus and the semiconductor industry.

“This is the very first silicon-proven memory buffer chip prototype capable of achieving the speeds required for the upcoming DDR5 standard. Data-intensive applications like Big Data analytics and machine learning will be key drivers for the adoption of DDR5, with enterprise close behind,” said Seraphin.

DDR5 DIMM Chipset illustration

“We are proud to provide an early path to adoption with the first working buffer chip prototype running at the anticipated performance of next-generation DDR5. This demonstrates our continued dedication to be first to market and remain on the leading edge of industry standards.”

As JEDEC recently confirmed, next-gen DDR5 memory will offer improved performance and power efficiency, providing double the bandwidth and density over DDR4, as well as improved channel efficiency.

“Server DIMM chipsets, like registered clock drivers and data buffers, will be critical to enabling higher memory capacities while maintaining peak performance,” Seraphin added. “Our server DIMM chip prototype leverages the signal integrity and low power, mixed-signal design expertise of Rambus to enable development of next-generation solutions for future data center workloads.”

For additional information about our server DIMM chipsets, please visit our DDR5 DIMM chipset page here.