Rambus and Northwest Logic certify HBM2 interoperability

This entry was posted on Monday, August 28th, 2017.

Rambus has validated interoperability between its HBM2 PHY and Northwest Logics’ HBM2 Memory Controller Core. The combined HBM2 solution is designed to support high-performance networking and server applications in the data center and communications markets that require the maximum amount of bandwidth available provided by HBM2.

According to Luc Seraphin, senior vice president and general manager of the Rambus Memory and Interfaces Division, the solution builds on the growing ecosystem of Rambus partner products that interoperate with its latest HBM2 PHY IP core.

“Our work with Northwest Logic gives Rambus the functionality to provide a verified solution that reduces the engineering workload and time to market for chip designers,” he explained.

“As Rambus extends its footprint in PHY support for leading-edge technologies, collaborative interoperability is essential for our end customers that demand early adoption.”

Memory interfaces are increasingly important for today’s data-heavy workloads, making the combination of Rambus HBM2 and Northwest Logic’ HBM2 Memory Controller core a natural fit to support customer demands on both sides.

“The Northwest Logic HBM2 Memory Controller Cores are optimized for use in both ASICs and FPGAs and support full-rate, half-rate and quarter-rate operations. The cores provide a solution that can be configured to exact customer requirements, are silicon-proven and verified with Rambus’ HBM2 PHY,” Seraphin added.

As Brian Daellenbach, president of Northwest Logic notes, the company’s HBM2 Memory Controller Core has been successfully deployed in a wide range of customer systems – demonstrating both high reliability and performance.

“We are excited to offer a complete HBM2 solution with Rambus, ensuring our customers achieve the best possible combined memory solution for their high data demands,” he stated.

The Rambus HBM2 PHY and Northwest Logic HBM2 Memory Controller are each fully JEDEC compliant with the HBM2 standard, allowing the PHY and memory controller to seamlessly interoperate.

The Rambus HBM2 PHY is a high-performance memory IP core that features reduced power consumption and a small form factor. It combines 2.5D packaging with a wider interface at a lower clock speed, delivering higher efficiency and lower power consumption compared to other memory solutions on the market.

Interested in learning more about our HBM PHYs? You can check out our product page and article archive on the subject here.